1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //mem status 30 val mem = OptionWrapper(params.isMemAddrIQ, new StatusMemPart) 31 //vector mem status 32 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 55 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 56 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 57 } 58 59 class StatusMemPart(implicit p:Parameters) extends Bundle { 60 val waitForSqIdx = new SqPtr // generated by store data valid check 61 val waitForRobIdx = new RobPtr // generated by store set 62 val waitForStd = Bool() 63 val strictWait = Bool() 64 val sqIdx = new SqPtr 65 } 66 67 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 68 val sqIdx = new SqPtr 69 val lqIdx = new LqPtr 70 val uopIdx = UopIdx() 71 } 72 73 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 74 val robIdx = new RobPtr 75 val resp = RespType() 76 val fuType = FuType() 77 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 78 } 79 80 object RespType { 81 def apply() = UInt(2.W) 82 83 def isBlocked(resp: UInt) = { 84 resp === block 85 } 86 87 def succeed(resp: UInt) = { 88 resp === success 89 } 90 91 val block = "b00".U 92 val uncertain = "b01".U 93 val success = "b11".U 94 } 95 96 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 97 val status = new Status() 98 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 99 val payload = new DynInst() 100 } 101 102 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 103 val flush = Flipped(ValidIO(new Redirect)) 104 val enq = Flipped(ValidIO(new EntryBundle)) 105 //wakeup 106 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 107 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 108 //cancel 109 val og0Cancel = Input(ExuOH(backendParams.numExu)) 110 val og1Cancel = Input(ExuOH(backendParams.numExu)) 111 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 112 //deq sel 113 val deqSel = Input(Bool()) 114 val deqPortIdxWrite = Input(UInt(1.W)) 115 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 116 //trans sel 117 val transSel = Input(Bool()) 118 // mem only 119 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 120 val stIssuePtr = Input(new SqPtr) 121 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 122 }) 123 // vector mem only 124 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 125 val sqDeqPtr = Input(new SqPtr) 126 val lqDeqPtr = Input(new LqPtr) 127 }) 128 } 129 130 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 131 //status 132 val valid = Output(Bool()) 133 val canIssue = Output(Bool()) 134 val fuType = Output(FuType()) 135 val robIdx = Output(new RobPtr) 136 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 137 //src 138 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 139 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 140 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 141 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 142 //deq 143 val isFirstIssue = Output(Bool()) 144 val entry = ValidIO(new EntryBundle) 145 val deqPortIdxRead = Output(UInt(1.W)) 146 val issueTimerRead = Output(UInt(2.W)) 147 //trans 148 val enqReady = Output(Bool()) 149 val transEntry = ValidIO(new EntryBundle) 150 // debug 151 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 152 val entryInValid = Output(Bool()) 153 val entryOutDeqValid = Output(Bool()) 154 val entryOutTransValid = Output(Bool()) 155 } 156 157 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 158 val validRegNext = Bool() 159 val flushed = Bool() 160 val clear = Bool() 161 val canIssue = Bool() 162 val enqReady = Bool() 163 val deqSuccess = Bool() 164 val srcWakeup = Vec(params.numRegSrc, Bool()) 165 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 166 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 167 val srcCancelVec = Vec(params.numRegSrc, Bool()) 168 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 169 } 170 171 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 172 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 173 common.flushed := status.robIdx.needFlush(commonIn.flush) 174 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 175 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 176 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 177 common.canIssue := validReg && status.canIssue 178 common.enqReady := !validReg || common.clear 179 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 180 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 181 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 182 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 183 srcCancel := srcLoadCancel || ldTransCancel 184 } 185 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 186 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 187 if(params.hasIQWakeUp) { 188 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 189 } else { 190 loadDependencyOut := loadDependency 191 } 192 193 } 194 if(isEnq) { 195 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 196 } else { 197 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 198 } 199 } 200 201 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 202 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 203 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 204 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 205 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 206 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 207 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 208 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 209 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 210 val cancelVec = Vec(params.numRegSrc, Bool()) 211 val canIssueBypass = Bool() 212 } 213 214 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 215 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 216 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 217 ).toSeq.transpose 218 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 219 220 hasIQWakeupGet.cancelVec := common.srcCancelVec 221 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 222 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 223 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 224 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 225 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 226 case (exuOH, regExuOH) => 227 exuOH := 0.U.asTypeOf(exuOH) 228 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 229 } 230 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 231 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 232 if(isEnq) { 233 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 234 } else { 235 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 236 } 237 } 238 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 239 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 240 wakeupVec.asUInt.orR | state 241 }).asUInt.andR 242 } 243 244 245 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 246 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 247 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 248 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 249 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 250 case ((dep, originalDep), deqPortIdx) => 251 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 252 dep := (originalDep << 2).asUInt | 2.U 253 else 254 dep := originalDep << 1 255 } 256 } 257 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 258 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 259 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 260 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 261 case ((dep, originalDep), deqPortIdx) => 262 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 263 dep := (originalDep << 1).asUInt | 1.U 264 else 265 dep := originalDep 266 } 267 } 268 } 269 270 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 271 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 272 val cancelByLd = common.srcCancelVec.asUInt.orR 273 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 274 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 275 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 276 entryUpdate.status.robIdx := status.robIdx 277 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 278 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 279 val cancel = common.srcCancelVec(srcIdx) 280 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 281 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 282 val wakeup = common.srcWakeup(srcIdx) 283 srcStatusNext.psrc := srcStatus.psrc 284 srcStatusNext.srcType := srcStatus.srcType 285 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 286 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, DataSource.reg) 287 if(params.hasIQWakeUp) { 288 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 289 // T0: waked up by IQ, T1: reset timer as 1 290 wakeupByIQ -> 2.U, 291 // do not overflow 292 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 293 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 294 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 295 )) 296 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 297 srcStatusNext.srcLoadDependency := 298 Mux(wakeup, 299 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 300 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 301 } else { 302 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 303 } 304 } 305 entryUpdate.status.blocked := false.B 306 entryUpdate.status.issued := MuxCase(status.issued, Seq( 307 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 308 commonIn.deqSel -> true.B, 309 !status.srcReady -> false.B, 310 )) 311 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 312 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 313 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 314 entryUpdate.imm.foreach(_ := entryReg.imm.get) 315 entryUpdate.payload := entryReg.payload 316 if (params.isVecMemIQ) { 317 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 318 } 319 } 320 321 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 322 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 323 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 324 commonOut.valid := validReg 325 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 326 else common.canIssue && !common.flushed) 327 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 328 commonOut.robIdx := status.robIdx 329 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 330 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 331 } 332 commonOut.isFirstIssue := !status.firstIssue 333 commonOut.entry.valid := validReg 334 commonOut.entry.bits := entryReg 335 if(isEnq) { 336 commonOut.entry.bits.status := status 337 } 338 commonOut.issueTimerRead := status.issueTimer 339 commonOut.deqPortIdxRead := status.deqPortIdx 340 if(params.hasIQWakeUp) { 341 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 342 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 343 else VecInit(srcWakeupExuOH)) 344 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 345 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 346 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 347 } 348 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 349 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 350 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 351 status.srcStatus(srcIdx).srcLoadDependency) 352 else status.srcStatus(srcIdx).srcLoadDependency) 353 } 354 } else { 355 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 356 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 357 } 358 } 359 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 360 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 361 common.srcLoadDependencyOut(srcIdx), 362 status.srcStatus(srcIdx).srcLoadDependency) 363 else status.srcStatus(srcIdx).srcLoadDependency) 364 } 365 commonOut.enqReady := common.enqReady 366 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 367 commonOut.transEntry.bits := entryUpdate 368 // debug 369 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 370 commonOut.entryInValid := commonIn.enq.valid 371 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 372 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 373 if (params.isVecMemIQ) { 374 commonOut.uopIdx.get := status.vecMem.get.uopIdx 375 } 376 } 377 378 def EntryMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 379 val enqValid = if(isEnq) commonIn.enq.valid && common.enqReady 380 else commonIn.enq.valid 381 val fromMem = commonIn.fromMem.get 382 val memStatus = entryReg.status.mem.get 383 val memStatusNext = entryRegNext.status.mem.get 384 val memStatusUpdate = entryUpdate.status.mem.get 385 386 when(enqValid) { 387 memStatusNext.waitForSqIdx := commonIn.enq.bits.status.mem.get.waitForSqIdx 388 // update by lfst at dispatch stage 389 memStatusNext.waitForRobIdx := commonIn.enq.bits.status.mem.get.waitForRobIdx 390 // new load inst don't known if it is blocked by store data ahead of it 391 memStatusNext.waitForStd := false.B 392 // update by ssit at rename stage 393 memStatusNext.strictWait := commonIn.enq.bits.status.mem.get.strictWait 394 memStatusNext.sqIdx := commonIn.enq.bits.status.mem.get.sqIdx 395 }.otherwise { 396 memStatusNext := memStatusUpdate 397 } 398 399 // load cannot be issued before older store, unless meet some condition 400 val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr) 401 402 403 val staWaitedReleased = Cat( 404 fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value) 405 ).orR 406 val stdWaitedReleased = Cat( 407 fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value) 408 ).orR 409 val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait 410 val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd 411 val waitStd = !olderStdReady 412 val waitSta = !olderStaNotViolate 413 414 memStatusUpdate := memStatus 415 416 val shouldBlock = Mux(enqValid, commonIn.enq.bits.status.blocked, entryReg.status.blocked) 417 val blockNotReleased = waitStd || waitSta 418 entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore 419 entryRegNext.status.blocked := entryUpdate.status.blocked 420 } 421 422 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 423 val origExuOH = 0.U.asTypeOf(exuOH) 424 when(wakeupByIQOH.asUInt.orR) { 425 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 426 }.elsewhen(wakeup) { 427 origExuOH := 0.U.asTypeOf(origExuOH) 428 }.otherwise { 429 origExuOH := regSrcExuOH 430 } 431 exuOH := 0.U.asTypeOf(exuOH) 432 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 433 } 434 435 object IQFuType { 436 def num = FuType.num 437 438 def apply() = Vec(num, Bool()) 439 440 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 441 val res = 0.U.asTypeOf(fuType) 442 fus.foreach(x => res(x.id) := fuType(x.id)) 443 res 444 } 445 } 446} 447