1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //vector mem status 30 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 31 32 def srcReady: Bool = { 33 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 34 } 35 36 def canIssue: Bool = { 37 srcReady && !issued && !blocked 38 } 39 40 def mergedLoadDependency: Vec[UInt] = { 41 srcStatus.map(_.srcLoadDependency).reduce({ 42 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 43 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 44 } 45 } 46 47 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 48 val psrc = UInt(params.rdPregIdxWidth.W) 49 val srcType = SrcType() 50 val srcState = SrcState() 51 val dataSources = DataSource() 52 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 53 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 54 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 55 } 56 57 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 58 val sqIdx = new SqPtr 59 val lqIdx = new LqPtr 60 } 61 62 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 63 val robIdx = new RobPtr 64 val resp = RespType() 65 val fuType = FuType() 66 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 67 } 68 69 object RespType { 70 def apply() = UInt(2.W) 71 72 def isBlocked(resp: UInt) = { 73 resp === block 74 } 75 76 def succeed(resp: UInt) = { 77 resp === success 78 } 79 80 val block = "b00".U 81 val uncertain = "b01".U 82 val success = "b11".U 83 } 84 85 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 86 val status = new Status() 87 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 88 val payload = new DynInst() 89 } 90 91 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 92 val flush = Flipped(ValidIO(new Redirect)) 93 val enq = Flipped(ValidIO(new EntryBundle)) 94 //wakeup 95 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 96 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 97 //cancel 98 val og0Cancel = Input(ExuOH(backendParams.numExu)) 99 val og1Cancel = Input(ExuOH(backendParams.numExu)) 100 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 101 //deq sel 102 val deqSel = Input(Bool()) 103 val deqPortIdxWrite = Input(UInt(1.W)) 104 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 105 //trans sel 106 val transSel = Input(Bool()) 107 // vector mem only 108 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 109 val sqDeqPtr = Input(new SqPtr) 110 val lqDeqPtr = Input(new LqPtr) 111 }) 112 } 113 114 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 115 //status 116 val valid = Output(Bool()) 117 val canIssue = Output(Bool()) 118 val fuType = Output(FuType()) 119 val robIdx = Output(new RobPtr) 120 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 121 //src 122 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 123 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 124 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 125 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 126 //deq 127 val isFirstIssue = Output(Bool()) 128 val entry = ValidIO(new EntryBundle) 129 val deqPortIdxRead = Output(UInt(1.W)) 130 val issueTimerRead = Output(UInt(2.W)) 131 //trans 132 val enqReady = Output(Bool()) 133 val transEntry = ValidIO(new EntryBundle) 134 // debug 135 val entryInValid = Output(Bool()) 136 val entryOutDeqValid = Output(Bool()) 137 val entryOutTransValid = Output(Bool()) 138 val perfLdCancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 139 val perfOg0Cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 140 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 141 val perfWakeupByIQ = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 142 } 143 144 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 145 val validRegNext = Bool() 146 val flushed = Bool() 147 val clear = Bool() 148 val canIssue = Bool() 149 val enqReady = Bool() 150 val deqSuccess = Bool() 151 val srcWakeup = Vec(params.numRegSrc, Bool()) 152 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 153 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 154 val srcCancelVec = Vec(params.numRegSrc, Bool()) 155 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 156 } 157 158 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 159 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 160 common.flushed := status.robIdx.needFlush(commonIn.flush) 161 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 162 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 163 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 164 common.canIssue := validReg && status.canIssue 165 common.enqReady := !validReg || common.clear 166 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 167 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 168 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 169 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 170 srcCancel := srcLoadCancel || ldTransCancel 171 } 172 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 173 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 174 if(params.hasIQWakeUp) { 175 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 176 } else { 177 loadDependencyOut := loadDependency 178 } 179 180 } 181 if(isEnq) { 182 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 183 } else { 184 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 185 } 186 } 187 188 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 189 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 190 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 191 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 192 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 193 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 194 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 195 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 196 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 197 val cancelVec = Vec(params.numRegSrc, Bool()) 198 val canIssueBypass = Bool() 199 } 200 201 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 202 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 203 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 204 ).toSeq.transpose 205 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 206 207 hasIQWakeupGet.cancelVec := common.srcCancelVec 208 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 209 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 210 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 211 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 212 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 213 case (exuOH, regExuOH) => 214 exuOH := 0.U.asTypeOf(exuOH) 215 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 216 } 217 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 218 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 219 if(isEnq) { 220 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 221 } else { 222 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 223 } 224 } 225 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 226 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 227 wakeupVec.asUInt.orR | state 228 }).asUInt.andR 229 } 230 231 232 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 233 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 234 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 235 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 236 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 237 case ((dep, originalDep), deqPortIdx) => 238 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 239 dep := 2.U 240 else 241 dep := originalDep << 1 242 } 243 } 244 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 245 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 246 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 247 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 248 case ((dep, originalDep), deqPortIdx) => 249 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 250 dep := 1.U 251 else 252 dep := originalDep 253 } 254 } 255 } 256 257 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 258 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 259 val cancelByLd = common.srcCancelVec.asUInt.orR 260 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 261 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 262 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 263 entryUpdate.status.robIdx := status.robIdx 264 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 265 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 266 val cancel = common.srcCancelVec(srcIdx) 267 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 268 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 269 val wakeup = common.srcWakeup(srcIdx) 270 srcStatusNext.psrc := srcStatus.psrc 271 srcStatusNext.srcType := srcStatus.srcType 272 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 273 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, Mux(srcStatus.dataSources.readBypass, DataSource.reg, srcStatus.dataSources.value)) 274 if(params.hasIQWakeUp) { 275 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 276 // T0: waked up by IQ, T1: reset timer as 1 277 wakeupByIQ -> 2.U, 278 // do not overflow 279 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 280 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 281 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 282 )) 283 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 284 srcStatusNext.srcLoadDependency := 285 Mux(wakeup, 286 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 287 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 288 } else { 289 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 290 } 291 } 292 entryUpdate.status.blocked := false.B 293 entryUpdate.status.issued := MuxCase(status.issued, Seq( 294 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 295 commonIn.deqSel -> true.B, 296 !status.srcReady -> false.B, 297 )) 298 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 299 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b11".U)) 300 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 301 entryUpdate.imm.foreach(_ := entryReg.imm.get) 302 entryUpdate.payload := entryReg.payload 303 if (params.isVecMemIQ) { 304 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 305 } 306 } 307 308 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 309 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 310 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 311 commonOut.valid := validReg 312 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 313 else common.canIssue && !common.flushed) 314 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 315 commonOut.robIdx := status.robIdx 316 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 317 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 318 } 319 commonOut.isFirstIssue := !status.firstIssue 320 commonOut.entry.valid := validReg 321 commonOut.entry.bits := entryReg 322 if(isEnq) { 323 commonOut.entry.bits.status := status 324 } 325 commonOut.issueTimerRead := status.issueTimer 326 commonOut.deqPortIdxRead := status.deqPortIdx 327 if(params.hasIQWakeUp) { 328 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 329 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 330 else VecInit(srcWakeupExuOH)) 331 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 332 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 333 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 334 } 335 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 336 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 337 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 338 status.srcStatus(srcIdx).srcLoadDependency) 339 else status.srcStatus(srcIdx).srcLoadDependency) 340 } 341 } else { 342 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 343 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 344 } 345 } 346 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 347 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 348 common.srcLoadDependencyOut(srcIdx), 349 status.srcStatus(srcIdx).srcLoadDependency) 350 else status.srcStatus(srcIdx).srcLoadDependency) 351 } 352 commonOut.enqReady := common.enqReady 353 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 354 commonOut.transEntry.bits := entryUpdate 355 // debug 356 commonOut.entryInValid := commonIn.enq.valid 357 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 358 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 359 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 360 if (params.hasIQWakeUp) { 361 commonOut.perfLdCancel.get := hasIQWakeupGet.cancelVec.map(_ && validReg) 362 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 363 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 364 } 365 // vecMem 366 if (params.isVecMemIQ) { 367 commonOut.uopIdx.get := entryReg.payload.uopIdx 368 } 369 } 370 371 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 372 val fromLsq = commonIn.fromLsq.get 373 val vecMemStatus = entryReg.status.vecMem.get 374 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 375 vecMemStatusUpdate := vecMemStatus 376 377 val isLsqHead = { 378 entryReg.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr && 379 entryReg.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr 380 } 381 382 // update blocked 383 entryUpdate.status.blocked := !isLsqHead 384 } 385 386 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 387 val origExuOH = 0.U.asTypeOf(exuOH) 388 when(wakeupByIQOH.asUInt.orR) { 389 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 390 }.otherwise { 391 origExuOH := regSrcExuOH 392 } 393 exuOH := 0.U.asTypeOf(exuOH) 394 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 395 } 396 397 object IQFuType { 398 def num = FuType.num 399 400 def apply() = Vec(num, Bool()) 401 402 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 403 val res = 0.U.asTypeOf(fuType) 404 fus.foreach(x => res(x.id) := fuType(x.id)) 405 res 406 } 407 } 408} 409