1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import ujson.IndexedValue.True 7import utils.MathUtils 8import utility.{HasCircularQueuePtrHelper, XSError} 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Bundles.NumLsElem 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16 17object EntryBundles extends HasCircularQueuePtrHelper { 18 19 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 20 //basic status 21 val robIdx = new RobPtr 22 val fuType = IQFuType() 23 //src status 24 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 25 //issue status 26 val blocked = Bool() 27 val issued = Bool() 28 val firstIssue = Bool() 29 val issueTimer = UInt(2.W) 30 val deqPortIdx = UInt(1.W) 31 //vector mem status 32 val vecMem = Option.when(params.isVecMemIQ)(new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 55 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(ExuVec()) 56 //reg cache 57 val useRegCache = Option.when(params.needReadRegCache)(Bool()) 58 val regCacheIdx = Option.when(params.needReadRegCache)(UInt(RegCacheIdxWidth.W)) 59 } 60 61 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 62 val sqIdx = new SqPtr 63 val lqIdx = new LqPtr 64 val numLsElem = NumLsElem() 65 } 66 67 class EntryDeqRespBundle(implicit p: Parameters, val params: IssueBlockParams) extends XSBundle { 68 val robIdx = new RobPtr 69 val resp = RespType() 70 val fuType = FuType() 71 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 72 val sqIdx = Option.when(params.needFeedBackSqIdx)(new SqPtr()) 73 val lqIdx = Option.when(params.needFeedBackLqIdx)(new LqPtr()) 74 } 75 76 object RespType { 77 def apply() = UInt(2.W) 78 79 def isBlocked(resp: UInt) = { 80 resp === block 81 } 82 83 def succeed(resp: UInt) = { 84 resp === success 85 } 86 87 val block = "b00".U 88 val uncertain = "b01".U 89 val success = "b11".U 90 } 91 92 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 93 val status = new Status() 94 val imm = Option.when(params.needImm)(UInt((params.deqImmTypesMaxLen).W)) 95 val payload = new DynInst() 96 } 97 98 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 99 val flush = Flipped(ValidIO(new Redirect)) 100 val enq = Flipped(ValidIO(new EntryBundle)) 101 //wakeup 102 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 103 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 104 // vl 105 val vlFromIntIsZero = Input(Bool()) 106 val vlFromIntIsVlmax = Input(Bool()) 107 val vlFromVfIsZero = Input(Bool()) 108 val vlFromVfIsVlmax = Input(Bool()) 109 //cancel 110 val og0Cancel = Input(ExuVec()) 111 val og1Cancel = Input(ExuVec()) 112 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 113 //deq sel 114 val deqSel = Input(Bool()) 115 val deqPortIdxWrite = Input(UInt(1.W)) 116 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 117 //trans sel 118 val transSel = Input(Bool()) 119 // vector mem only 120 val fromLsq = Option.when(params.isVecMemIQ)(new Bundle { 121 val sqDeqPtr = Input(new SqPtr) 122 val lqDeqPtr = Input(new LqPtr) 123 }) 124 } 125 126 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 127 //status 128 val valid = Output(Bool()) 129 val issued = Output(Bool()) 130 val canIssue = Output(Bool()) 131 val fuType = Output(FuType()) 132 val robIdx = Output(new RobPtr) 133 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 134 //src 135 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 136 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(Vec(params.numRegSrc, Output(ExuVec()))) 137 //deq 138 val isFirstIssue = Output(Bool()) 139 val entry = ValidIO(new EntryBundle) 140 val cancelBypass = Output(Bool()) 141 val deqPortIdxRead = Output(UInt(1.W)) 142 val issueTimerRead = Output(UInt(2.W)) 143 //trans 144 val enqReady = Output(Bool()) 145 val transEntry = ValidIO(new EntryBundle) 146 // debug 147 val entryInValid = Output(Bool()) 148 val entryOutDeqValid = Output(Bool()) 149 val entryOutTransValid = Output(Bool()) 150 val perfLdCancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 151 val perfOg0Cancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 152 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 153 val perfWakeupByIQ = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 154 } 155 156 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 157 val validRegNext = Bool() 158 val flushed = Bool() 159 val clear = Bool() 160 val canIssue = Bool() 161 val enqReady = Bool() 162 val deqSuccess = Bool() 163 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 164 val vlWakeupByIntWb = Bool() 165 val vlWakeupByVfWb = Bool() 166 val srcCancelVec = Vec(params.numRegSrc, Bool()) 167 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 168 val srcLoadTransCancelVec = Vec(params.numRegSrc, Bool()) 169 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 170 } 171 172 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 173 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 174 common.flushed := status.robIdx.needFlush(commonIn.flush) 175 common.deqSuccess := (if (params.isVecMemIQ) status.issued else true.B) && 176 commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 177 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 178 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 179 if (params.numRegSrc == 5) { 180 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 181 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 182 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 183 } 184 else 185 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 186 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 187 common.canIssue := validReg && status.canIssue 188 common.enqReady := !validReg || commonIn.transSel 189 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 190 common.srcCancelVec.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case ((srcCancel, wakeUpByIQVec), srcIdx) => 191 common.srcLoadTransCancelVec(srcIdx) := (if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B) 192 common.srcLoadCancelVec(srcIdx) := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 193 srcCancel := common.srcLoadTransCancelVec(srcIdx) || common.srcLoadCancelVec(srcIdx) 194 } 195 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 196 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 197 } 198 if(isEnq) { 199 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 200 } else { 201 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 202 } 203 if (params.numRegSrc == 5) { 204 // only when numRegSrc == 5 need vl 205 val wakeUpFromVl = VecInit(commonIn.wakeUpFromWB.map{ bundle => 206 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 207 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 208 }) 209 var numVecWb = params.backendParam.getVfWBExeGroup.size 210 var numV0Wb = params.backendParam.getV0WBExeGroup.size 211 var intSchdVlWbPort = p(XSCoreParamsKey).intSchdVlWbPort 212 var vfSchdVlWbPort = p(XSCoreParamsKey).vfSchdVlWbPort 213 // int wb is first bit of vlwb, which is after vfwb and v0wb 214 common.vlWakeupByIntWb := wakeUpFromVl(numVecWb + numV0Wb + intSchdVlWbPort) 215 // vf wb is second bit of wb 216 common.vlWakeupByVfWb := wakeUpFromVl(numVecWb + numV0Wb + vfSchdVlWbPort) 217 } else { 218 common.vlWakeupByIntWb := false.B 219 common.vlWakeupByVfWb := false.B 220 } 221 } 222 223 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 224 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 225 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 226 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 227 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 228 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 229 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 230 val canIssueBypass = Bool() 231 } 232 233 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 234 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 235 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 236 if (params.numRegSrc == 5) { 237 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 238 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 239 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 240 } 241 else 242 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 243 }.toSeq.transpose 244 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 245 246 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 247 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 248 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 249 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 250 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 251 case (exuOH, regExuOH) => 252 exuOH := 0.U.asTypeOf(exuOH) 253 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 254 } 255 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 256 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 257 wakeupVec.asUInt.orR | state 258 }).asUInt.andR 259 } 260 261 262 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 263 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 264 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 265 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 266 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 267 case ((dep, originalDep), deqPortIdx) => 268 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 269 dep := 1.U 270 else 271 dep := originalDep << 1 272 } 273 } 274 } 275 276 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 277 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 278 OH.zip(allExuParams).map{case (oh,e) => 279 if (e.isVfExeUnit) oh else false.B 280 }.reduce(_ || _) 281 } 282 283 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 284 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 285 val cancelBypassVec = Wire(Vec(params.numRegSrc, Bool())) 286 val srcCancelByLoad = common.srcLoadCancelVec.asUInt.orR 287 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 288 entryUpdate.status.robIdx := status.robIdx 289 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 290 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 291 val srcLoadCancel = common.srcLoadCancelVec(srcIdx) 292 val loadTransCancel = common.srcLoadTransCancelVec(srcIdx) 293 val wakeupByWB = common.srcWakeupByWB(srcIdx) 294 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR && !loadTransCancel 295 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 296 val wakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 297 cancelBypassVec(srcIdx) := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, loadTransCancel, srcLoadCancel) 298 else srcLoadCancel) 299 300 val ignoreOldVd = Wire(Bool()) 301 val vlWakeUpByIntWb = common.vlWakeupByIntWb 302 val vlWakeUpByVfWb = common.vlWakeupByVfWb 303 val isDependOldVd = entryReg.payload.vpu.isDependOldVd 304 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 305 val vta = entryReg.payload.vpu.vta 306 val vma = entryReg.payload.vpu.vma 307 val vm = entryReg.payload.vpu.vm 308 val vlFromIntIsZero = commonIn.vlFromIntIsZero 309 val vlFromIntIsVlmax = commonIn.vlFromIntIsVlmax 310 val vlFromVfIsZero = commonIn.vlFromVfIsZero 311 val vlFromVfIsVlmax = commonIn.vlFromVfIsVlmax 312 val vlIsVlmax = (vlFromIntIsVlmax && vlWakeUpByIntWb) || (vlFromVfIsVlmax && vlWakeUpByVfWb) 313 val vlIsNonZero = (!vlFromIntIsZero && vlWakeUpByIntWb) || (!vlFromVfIsZero && vlWakeUpByVfWb) 314 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 315 val ignoreWhole = (vm =/= 0.U || vma) && vta 316 val srcIsVec = SrcType.isVp(srcStatus.srcType) 317 if (params.numVfSrc > 0 && srcIdx == 2) { 318 /** 319 * the src store the old vd, update it when vl is write back 320 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 321 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 322 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 323 */ 324 ignoreOldVd := srcIsVec && vlIsNonZero && !isDependOldVd && (ignoreTail || ignoreWhole) 325 } else { 326 ignoreOldVd := false.B 327 } 328 329 srcStatusNext.psrc := srcStatus.psrc 330 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 331 srcStatusNext.srcState := srcStatus.srcState & !srcLoadCancel | wakeupByWB | wakeupByIQ | ignoreOldVd 332 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 333 // Vf / Mem -> Vf 334 MuxCase(srcStatus.dataSources.value, Seq( 335 ignoreOldVd -> DataSource.imm, 336 (wakeupByIQ && wakeupByMemIQ) -> DataSource.bypass2, 337 (wakeupByIQ && !wakeupByMemIQ) -> DataSource.bypass, 338 srcStatus.dataSources.readBypass -> DataSource.bypass2, 339 srcStatus.dataSources.readBypass2 -> DataSource.reg, 340 )) 341 } 342 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 343 // Vf / Int -> Mem 344 MuxCase(srcStatus.dataSources.value, Seq( 345 wakeupByIQ -> DataSource.bypass, 346 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 347 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 348 srcStatus.dataSources.readBypass2 -> DataSource.reg, 349 )) 350 } 351 else { 352 MuxCase(srcStatus.dataSources.value, Seq( 353 ignoreOldVd -> DataSource.imm, 354 wakeupByIQ -> DataSource.bypass, 355 srcStatus.dataSources.readBypass -> DataSource.reg, 356 )) 357 }) 358 if(params.hasIQWakeUp) { 359 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 360 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 361 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 362 common.srcLoadDependencyNext(srcIdx)) 363 } else { 364 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 365 } 366 367 if (params.needReadRegCache) { 368 val wakeupSrcExuWriteRC = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.needWriteRegCache) 369 val wakeupRC = wakeupSrcExuWriteRC.map(_._1).fold(false.B)(_ || _) && SrcType.isXp(srcStatus.srcType) 370 val wakeupRCIdx = Mux1H(wakeupSrcExuWriteRC.map(_._1), wakeupSrcExuWriteRC.map(_._2.bits.rcDest.get)) 371 val replaceRC = wakeupSrcExuWriteRC.map(x => x._2.bits.rfWen && x._2.bits.rcDest.get === srcStatus.regCacheIdx.get).fold(false.B)(_ || _) 372 373 srcStatusNext.useRegCache.get := srcStatus.useRegCache.get && !(srcLoadCancel || replaceRC) || wakeupRC 374 srcStatusNext.regCacheIdx.get := Mux(wakeupRC, wakeupRCIdx, srcStatus.regCacheIdx.get) 375 } 376 } 377 entryUpdate.status.blocked := false.B 378 entryUpdate.status.issued := MuxCase(status.issued, Seq( 379 (commonIn.deqSel && !cancelBypassVec.asUInt.orR) -> true.B, 380 (srcCancelByLoad || respIssueFail) -> false.B, 381 )) 382 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 383 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 384 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 385 entryUpdate.imm.foreach(_ := entryReg.imm.get) 386 entryUpdate.payload := entryReg.payload 387 if (params.isVecMemIQ) { 388 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 389 } 390 } 391 392 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 393 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 394 commonOut.valid := validReg 395 commonOut.issued := entryReg.status.issued 396 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 397 else common.canIssue && !common.flushed) 398 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 399 commonOut.robIdx := status.robIdx 400 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 401 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 402 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 403 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 404 val useRegCache = status.srcStatus(srcIdx).useRegCache.getOrElse(false.B) && status.srcStatus(srcIdx).dataSources.readReg 405 dataSourceOut.value := (if (isComp) 406 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 407 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 408 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 409 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 410 )) 411 } else { 412 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 413 wakeupByIQWithoutCancel -> DataSource.forward, 414 useRegCache -> DataSource.regcache, 415 )) 416 } 417 else { 418 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 419 useRegCache -> DataSource.regcache, 420 )) 421 }) 422 } 423 commonOut.isFirstIssue := !status.firstIssue 424 commonOut.entry.valid := validReg 425 commonOut.entry.bits := entryReg 426 if(isEnq) { 427 commonOut.entry.bits.status := status 428 } 429 commonOut.issueTimerRead := status.issueTimer 430 commonOut.deqPortIdxRead := status.deqPortIdx 431 432 if(params.hasIQWakeUp) { 433 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 434 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 435 if (isComp) 436 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 437 else 438 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 439 } 440 } 441 442 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 443 if(params.hasIQWakeUp) { 444 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 445 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 446 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 447 wakeupSrcLoadDependencyNext(srcIdx), 448 common.srcLoadDependencyNext(srcIdx)) 449 else common.srcLoadDependencyNext(srcIdx)) 450 } 451 } else { 452 srcLoadDependencyOut := common.srcLoadDependencyNext 453 } 454 commonOut.cancelBypass := VecInit(hasIQWakeupGet.srcWakeupByIQWithoutCancel.zipWithIndex.map{ case (wakeupVec, srcIdx) => 455 if (isComp) Mux(wakeupVec.asUInt.orR, common.srcLoadTransCancelVec(srcIdx), common.srcLoadCancelVec(srcIdx)) 456 else common.srcLoadCancelVec(srcIdx) 457 }).asUInt.orR 458 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 459 ldOut := srcLoadDependencyOut(srcIdx) 460 } 461 462 commonOut.enqReady := common.enqReady 463 commonOut.transEntry.valid := validReg && !common.flushed && !status.issued 464 commonOut.transEntry.bits := entryUpdate 465 // debug 466 commonOut.entryInValid := commonIn.enq.valid 467 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 468 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 469 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 470 if (params.hasIQWakeUp) { 471 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 472 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 473 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 474 } 475 // vecMem 476 if (params.isVecMemIQ) { 477 commonOut.uopIdx.get := entryReg.payload.uopIdx 478 } 479 } 480 481 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 482 val fromLsq = commonIn.fromLsq.get 483 val vecMemStatus = entryReg.status.vecMem.get 484 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 485 vecMemStatusUpdate := vecMemStatus 486 487 val isFirstLoad = entryReg.status.vecMem.get.lqIdx === fromLsq.lqDeqPtr 488 489 val isVleff = entryReg.payload.vpu.isVleff 490 // update blocked 491 entryUpdate.status.blocked := !isFirstLoad && isVleff 492 } 493 494 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 495 val origExuOH = Wire(chiselTypeOf(exuOH)) 496 when(wakeupByIQOH.asUInt.orR) { 497 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 498 }.otherwise { 499 origExuOH := regSrcExuOH 500 } 501 exuOH := 0.U.asTypeOf(exuOH) 502 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 503 } 504 505 object IQFuType { 506 def num = FuType.num 507 508 def apply() = Vec(num, Bool()) 509 510 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 511 val res = WireDefault(0.U.asTypeOf(fuType)) 512 fus.foreach(x => res(x.id) := fuType(x.id)) 513 res 514 } 515 } 516 517 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 518 //wakeup 519 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 520 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 521 //cancel 522 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 523 val og0Cancel = Input(ExuVec()) 524 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 525 } 526 527 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 528 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 529 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 530 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 531 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 532 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 533 } 534 535 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 536 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 537 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 538 if (i == 3) 539 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 540 else if (i == 4) 541 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 542 else 543 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 544 }.reduce(_ || _) 545 } 546 547 if (params.hasIQWakeUp) { 548 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 549 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 550 if (params.numRegSrc == 5) { 551 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 552 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 553 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 554 } 555 else 556 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 557 }.toIndexedSeq.transpose 558 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 559 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 560 } else { 561 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 562 } 563 564 if (params.hasIQWakeUp) { 565 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 566 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 567 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 568 } 569 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 570 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 571 } 572 } else { 573 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 574 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 575 } 576 577 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 578 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 579 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 580 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 581 dp := 1.U << (delay - 1) 582 else 583 dp := ldp << delay 584 } 585 } 586 } 587} 588