1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //vector mem status 30 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 31 32 def srcReady: Bool = { 33 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 34 } 35 36 def canIssue: Bool = { 37 srcReady && !issued && !blocked 38 } 39 40 def mergedLoadDependency: Vec[UInt] = { 41 srcStatus.map(_.srcLoadDependency).reduce({ 42 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 43 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 44 } 45 } 46 47 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 48 val psrc = UInt(params.rdPregIdxWidth.W) 49 val srcType = SrcType() 50 val srcState = SrcState() 51 val dataSources = DataSource() 52 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 53 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 54 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 55 } 56 57 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 58 val sqIdx = new SqPtr 59 val lqIdx = new LqPtr 60 } 61 62 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 63 val robIdx = new RobPtr 64 val resp = RespType() 65 val fuType = FuType() 66 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 67 } 68 69 object RespType { 70 def apply() = UInt(2.W) 71 72 def isBlocked(resp: UInt) = { 73 resp === block 74 } 75 76 def succeed(resp: UInt) = { 77 resp === success 78 } 79 80 val block = "b00".U 81 val uncertain = "b01".U 82 val success = "b11".U 83 } 84 85 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 86 val status = new Status() 87 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 88 val payload = new DynInst() 89 } 90 91 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 92 val flush = Flipped(ValidIO(new Redirect)) 93 val enq = Flipped(ValidIO(new EntryBundle)) 94 //wakeup 95 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 96 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 97 //cancel 98 val og0Cancel = Input(ExuOH(backendParams.numExu)) 99 val og1Cancel = Input(ExuOH(backendParams.numExu)) 100 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 101 //deq sel 102 val deqSel = Input(Bool()) 103 val deqPortIdxWrite = Input(UInt(1.W)) 104 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 105 //trans sel 106 val transSel = Input(Bool()) 107 // vector mem only 108 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 109 val sqDeqPtr = Input(new SqPtr) 110 val lqDeqPtr = Input(new LqPtr) 111 }) 112 } 113 114 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 115 //status 116 val valid = Output(Bool()) 117 val canIssue = Output(Bool()) 118 val fuType = Output(FuType()) 119 val robIdx = Output(new RobPtr) 120 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 121 //src 122 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 123 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 124 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 125 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 126 //deq 127 val isFirstIssue = Output(Bool()) 128 val entry = ValidIO(new EntryBundle) 129 val deqPortIdxRead = Output(UInt(1.W)) 130 val issueTimerRead = Output(UInt(2.W)) 131 //trans 132 val enqReady = Output(Bool()) 133 val transEntry = ValidIO(new EntryBundle) 134 // debug 135 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 136 val entryInValid = Output(Bool()) 137 val entryOutDeqValid = Output(Bool()) 138 val entryOutTransValid = Output(Bool()) 139 } 140 141 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 142 val validRegNext = Bool() 143 val flushed = Bool() 144 val clear = Bool() 145 val canIssue = Bool() 146 val enqReady = Bool() 147 val deqSuccess = Bool() 148 val srcWakeup = Vec(params.numRegSrc, Bool()) 149 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 150 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 151 val srcCancelVec = Vec(params.numRegSrc, Bool()) 152 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 153 } 154 155 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 156 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 157 common.flushed := status.robIdx.needFlush(commonIn.flush) 158 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 159 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 160 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 161 common.canIssue := validReg && status.canIssue 162 common.enqReady := !validReg || common.clear 163 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 164 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 165 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 166 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 167 srcCancel := srcLoadCancel || ldTransCancel 168 } 169 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 170 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 171 if(params.hasIQWakeUp) { 172 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 173 } else { 174 loadDependencyOut := loadDependency 175 } 176 177 } 178 if(isEnq) { 179 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 180 } else { 181 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 182 } 183 } 184 185 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 186 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 187 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 188 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 189 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 190 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 191 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 192 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 193 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 194 val cancelVec = Vec(params.numRegSrc, Bool()) 195 val canIssueBypass = Bool() 196 } 197 198 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 199 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 200 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 201 ).toSeq.transpose 202 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 203 204 hasIQWakeupGet.cancelVec := common.srcCancelVec 205 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 206 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 207 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 208 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 209 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 210 case (exuOH, regExuOH) => 211 exuOH := 0.U.asTypeOf(exuOH) 212 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 213 } 214 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 215 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 216 if(isEnq) { 217 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 218 } else { 219 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 220 } 221 } 222 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 223 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 224 wakeupVec.asUInt.orR | state 225 }).asUInt.andR 226 } 227 228 229 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 230 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 231 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 232 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 233 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 234 case ((dep, originalDep), deqPortIdx) => 235 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 236 dep := (originalDep << 2).asUInt | 2.U 237 else 238 dep := originalDep << 1 239 } 240 } 241 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 242 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 243 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 244 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 245 case ((dep, originalDep), deqPortIdx) => 246 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 247 dep := (originalDep << 1).asUInt | 1.U 248 else 249 dep := originalDep 250 } 251 } 252 } 253 254 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 255 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 256 val cancelByLd = common.srcCancelVec.asUInt.orR 257 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 258 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 259 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 260 entryUpdate.status.robIdx := status.robIdx 261 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 262 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 263 val cancel = common.srcCancelVec(srcIdx) 264 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 265 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 266 val wakeup = common.srcWakeup(srcIdx) 267 srcStatusNext.psrc := srcStatus.psrc 268 srcStatusNext.srcType := srcStatus.srcType 269 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 270 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, Mux(srcStatus.dataSources.readBypass, DataSource.reg, srcStatus.dataSources.value)) 271 if(params.hasIQWakeUp) { 272 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 273 // T0: waked up by IQ, T1: reset timer as 1 274 wakeupByIQ -> 2.U, 275 // do not overflow 276 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 277 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 278 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 279 )) 280 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 281 srcStatusNext.srcLoadDependency := 282 Mux(wakeup, 283 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 284 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 285 } else { 286 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 287 } 288 } 289 entryUpdate.status.blocked := false.B 290 entryUpdate.status.issued := MuxCase(status.issued, Seq( 291 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 292 commonIn.deqSel -> true.B, 293 !status.srcReady -> false.B, 294 )) 295 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 296 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 297 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 298 entryUpdate.imm.foreach(_ := entryReg.imm.get) 299 entryUpdate.payload := entryReg.payload 300 if (params.isVecMemIQ) { 301 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 302 } 303 } 304 305 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 306 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 307 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 308 commonOut.valid := validReg 309 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 310 else common.canIssue && !common.flushed) 311 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 312 commonOut.robIdx := status.robIdx 313 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 314 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 315 } 316 commonOut.isFirstIssue := !status.firstIssue 317 commonOut.entry.valid := validReg 318 commonOut.entry.bits := entryReg 319 if(isEnq) { 320 commonOut.entry.bits.status := status 321 } 322 commonOut.issueTimerRead := status.issueTimer 323 commonOut.deqPortIdxRead := status.deqPortIdx 324 if(params.hasIQWakeUp) { 325 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 326 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 327 else VecInit(srcWakeupExuOH)) 328 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 329 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 330 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 331 } 332 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 333 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 334 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 335 status.srcStatus(srcIdx).srcLoadDependency) 336 else status.srcStatus(srcIdx).srcLoadDependency) 337 } 338 } else { 339 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 340 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 341 } 342 } 343 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 344 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 345 common.srcLoadDependencyOut(srcIdx), 346 status.srcStatus(srcIdx).srcLoadDependency) 347 else status.srcStatus(srcIdx).srcLoadDependency) 348 } 349 commonOut.enqReady := common.enqReady 350 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 351 commonOut.transEntry.bits := entryUpdate 352 // debug 353 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 354 commonOut.entryInValid := commonIn.enq.valid 355 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 356 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 357 if (params.isVecMemIQ) { 358 commonOut.uopIdx.get := entryReg.payload.uopIdx 359 } 360 } 361 362 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 363 val fromLsq = commonIn.fromLsq.get 364 val vecMemStatus = entryReg.status.vecMem.get 365 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 366 vecMemStatusUpdate := vecMemStatus 367 368 val isLsqHead = { 369 entryReg.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr && 370 entryReg.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr 371 } 372 373 // update blocked 374 entryUpdate.status.blocked := !isLsqHead 375 } 376 377 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 378 val origExuOH = 0.U.asTypeOf(exuOH) 379 when(wakeupByIQOH.asUInt.orR) { 380 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 381 }.otherwise { 382 origExuOH := regSrcExuOH 383 } 384 exuOH := 0.U.asTypeOf(exuOH) 385 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 386 } 387 388 object IQFuType { 389 def num = FuType.num 390 391 def apply() = Vec(num, Bool()) 392 393 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 394 val res = 0.U.asTypeOf(fuType) 395 fus.foreach(x => res(x.id) := fuType(x.id)) 396 res 397 } 398 } 399} 400