1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //vector mem status 30 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 31 32 def srcReady: Bool = { 33 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 34 } 35 36 def canIssue: Bool = { 37 srcReady && !issued && !blocked 38 } 39 40 def mergedLoadDependency: Vec[UInt] = { 41 srcStatus.map(_.srcLoadDependency).reduce({ 42 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 43 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 44 } 45 } 46 47 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 48 val psrc = UInt(params.rdPregIdxWidth.W) 49 val srcType = SrcType() 50 val srcState = SrcState() 51 val dataSources = DataSource() 52 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 53 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 54 } 55 56 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 57 val sqIdx = new SqPtr 58 val lqIdx = new LqPtr 59 } 60 61 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 62 val robIdx = new RobPtr 63 val resp = RespType() 64 val fuType = FuType() 65 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 66 } 67 68 object RespType { 69 def apply() = UInt(2.W) 70 71 def isBlocked(resp: UInt) = { 72 resp === block 73 } 74 75 def succeed(resp: UInt) = { 76 resp === success 77 } 78 79 val block = "b00".U 80 val uncertain = "b01".U 81 val success = "b11".U 82 } 83 84 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 85 val status = new Status() 86 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 87 val payload = new DynInst() 88 } 89 90 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 91 val flush = Flipped(ValidIO(new Redirect)) 92 val enq = Flipped(ValidIO(new EntryBundle)) 93 //wakeup 94 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 95 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 96 //cancel 97 val og0Cancel = Input(ExuOH(backendParams.numExu)) 98 val og1Cancel = Input(ExuOH(backendParams.numExu)) 99 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 100 //deq sel 101 val deqSel = Input(Bool()) 102 val deqPortIdxWrite = Input(UInt(1.W)) 103 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 104 //trans sel 105 val transSel = Input(Bool()) 106 // vector mem only 107 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 108 val sqDeqPtr = Input(new SqPtr) 109 val lqDeqPtr = Input(new LqPtr) 110 }) 111 } 112 113 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 114 //status 115 val valid = Output(Bool()) 116 val canIssue = Output(Bool()) 117 val fuType = Output(FuType()) 118 val robIdx = Output(new RobPtr) 119 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 120 //src 121 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 122 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 123 //deq 124 val isFirstIssue = Output(Bool()) 125 val entry = ValidIO(new EntryBundle) 126 val cancelBypass = Output(Bool()) 127 val deqPortIdxRead = Output(UInt(1.W)) 128 val issueTimerRead = Output(UInt(2.W)) 129 //trans 130 val enqReady = Output(Bool()) 131 val transEntry = ValidIO(new EntryBundle) 132 // debug 133 val entryInValid = Output(Bool()) 134 val entryOutDeqValid = Output(Bool()) 135 val entryOutTransValid = Output(Bool()) 136 val perfLdCancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 137 val perfOg0Cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 138 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 139 val perfWakeupByIQ = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 140 } 141 142 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 143 val validRegNext = Bool() 144 val flushed = Bool() 145 val clear = Bool() 146 val canIssue = Bool() 147 val enqReady = Bool() 148 val deqSuccess = Bool() 149 val srcWakeup = Vec(params.numRegSrc, Bool()) 150 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 151 val srcCancelVec = Vec(params.numRegSrc, Bool()) 152 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 153 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 154 } 155 156 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 157 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 158 common.flushed := status.robIdx.needFlush(commonIn.flush) 159 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 160 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 161 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 162 common.canIssue := validReg && status.canIssue 163 common.enqReady := !validReg || common.clear 164 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 165 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 166 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 167 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 168 srcCancel := srcLoadCancel || ldTransCancel 169 } 170 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 171 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 172 } 173 if(isEnq) { 174 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 175 } else { 176 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 177 } 178 } 179 180 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 181 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 182 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 183 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 184 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 185 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 186 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 187 val canIssueBypass = Bool() 188 } 189 190 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 191 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 192 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 193 ).toSeq.transpose 194 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 195 196 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 197 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 198 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 199 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 200 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 201 case (exuOH, regExuOH) => 202 exuOH := 0.U.asTypeOf(exuOH) 203 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 204 } 205 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 206 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 207 wakeupVec.asUInt.orR | state 208 }).asUInt.andR 209 } 210 211 212 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 213 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 214 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 215 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 216 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 217 case ((dep, originalDep), deqPortIdx) => 218 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 219 dep := 1.U 220 else 221 dep := originalDep << 1 222 } 223 } 224 } 225 226 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 227 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 228 OH.zip(allExuParams).map{case (oh,e) => 229 if (e.isVfExeUnit) oh else false.B 230 }.reduce(_ || _) 231 } 232 233 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 234 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 235 val cancelByLd = common.srcCancelVec.asUInt.orR 236 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 237 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 238 entryUpdate.status.robIdx := status.robIdx 239 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 240 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 241 val cancel = common.srcCancelVec(srcIdx) 242 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 243 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 244 val wakeup = common.srcWakeup(srcIdx) 245 srcStatusNext.psrc := srcStatus.psrc 246 srcStatusNext.srcType := srcStatus.srcType 247 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 248 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 249 // Vf / Mem -> Vf 250 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 251 MuxCase(srcStatus.dataSources.value, Seq( 252 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 253 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 254 srcStatus.dataSources.readBypass -> DataSource.bypass2, 255 srcStatus.dataSources.readBypass2 -> DataSource.reg, 256 )) 257 } 258 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 259 // Vf / Int -> Mem 260 MuxCase(srcStatus.dataSources.value, Seq( 261 wakeupByIQ -> DataSource.bypass, 262 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 263 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 264 srcStatus.dataSources.readBypass2 -> DataSource.reg, 265 )) 266 } 267 else { 268 MuxCase(srcStatus.dataSources.value, Seq( 269 wakeupByIQ -> DataSource.bypass, 270 srcStatus.dataSources.readBypass -> DataSource.reg, 271 )) 272 }) 273 if(params.hasIQWakeUp) { 274 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 275 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 276 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 277 common.srcLoadDependencyNext(srcIdx)) 278 } else { 279 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 280 } 281 } 282 entryUpdate.status.blocked := false.B 283 entryUpdate.status.issued := MuxCase(status.issued, Seq( 284 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 285 commonIn.deqSel -> true.B, 286 !status.srcReady -> false.B, 287 )) 288 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 289 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b11".U)) 290 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 291 entryUpdate.imm.foreach(_ := entryReg.imm.get) 292 entryUpdate.payload := entryReg.payload 293 if (params.isVecMemIQ) { 294 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 295 } 296 } 297 298 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 299 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 300 commonOut.valid := validReg 301 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 302 else common.canIssue && !common.flushed) 303 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 304 commonOut.robIdx := status.robIdx 305 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 306 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 307 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 308 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 309 dataSourceOut.value := (if (isComp) 310 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 311 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 312 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 313 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 314 )) 315 } else { 316 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 317 wakeupByIQWithoutCancel -> DataSource.forward, 318 )) 319 } 320 else 321 status.srcStatus(srcIdx).dataSources.value) 322 } 323 commonOut.isFirstIssue := !status.firstIssue 324 commonOut.entry.valid := validReg 325 commonOut.entry.bits := entryReg 326 if(isEnq) { 327 commonOut.entry.bits.status := status 328 } 329 commonOut.issueTimerRead := status.issueTimer 330 commonOut.deqPortIdxRead := status.deqPortIdx 331 332 if(params.hasIQWakeUp) { 333 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 334 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 335 if (isComp) 336 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 337 else 338 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 339 } 340 } 341 342 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 343 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 344 if(params.hasIQWakeUp) { 345 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 346 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 347 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 348 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 349 wakeupSrcLoadDependency(srcIdx), 350 status.srcStatus(srcIdx).srcLoadDependency) 351 else status.srcStatus(srcIdx).srcLoadDependency) 352 } 353 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 354 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 355 wakeupSrcLoadDependencyNext(srcIdx), 356 common.srcLoadDependencyNext(srcIdx)) 357 else common.srcLoadDependencyNext(srcIdx)) 358 } 359 } else { 360 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 361 srcLoadDependencyOut := common.srcLoadDependencyNext 362 } 363 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 364 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 365 ldOut := srcLoadDependencyOut(srcIdx) 366 } 367 368 commonOut.enqReady := common.enqReady 369 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 370 commonOut.transEntry.bits := entryUpdate 371 // debug 372 commonOut.entryInValid := commonIn.enq.valid 373 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 374 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 375 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 376 if (params.hasIQWakeUp) { 377 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 378 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 379 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 380 } 381 // vecMem 382 if (params.isVecMemIQ) { 383 commonOut.uopIdx.get := entryReg.payload.uopIdx 384 } 385 } 386 387 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 388 val fromLsq = commonIn.fromLsq.get 389 val vecMemStatus = entryReg.status.vecMem.get 390 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 391 vecMemStatusUpdate := vecMemStatus 392 393 val isLsqHead = { 394 entryReg.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr && 395 entryReg.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr 396 } 397 398 // update blocked 399 entryUpdate.status.blocked := !isLsqHead 400 } 401 402 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 403 val origExuOH = 0.U.asTypeOf(exuOH) 404 when(wakeupByIQOH.asUInt.orR) { 405 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 406 }.otherwise { 407 origExuOH := regSrcExuOH 408 } 409 exuOH := 0.U.asTypeOf(exuOH) 410 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 411 } 412 413 object IQFuType { 414 def num = FuType.num 415 416 def apply() = Vec(num, Bool()) 417 418 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 419 val res = 0.U.asTypeOf(fuType) 420 fus.foreach(x => res(x.id) := fuType(x.id)) 421 res 422 } 423 } 424 425 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 426 //wakeup 427 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 428 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 429 //cancel 430 val og0Cancel = Input(ExuOH(backendParams.numExu)) 431 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 432 } 433 434 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 435 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 436 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 437 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 438 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 439 } 440 441 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 442 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 443 wakeup := enqDelayIn.wakeUpFromWB.map(x => x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 444 ).reduce(_ || _) 445 } 446 447 if (params.hasIQWakeUp) { 448 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map( x => 449 x.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 450 ).toIndexedSeq.transpose 451 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 452 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 453 } else { 454 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 455 } 456 457 if (params.hasIQWakeUp) { 458 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 459 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 460 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 461 } 462 } else { 463 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 464 } 465 466 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 467 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 468 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 469 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 470 dp := 1.U << (delay - 1) 471 else 472 dp := ldp << delay 473 } 474 } 475 } 476} 477