1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import ujson.IndexedValue.True 7import utils.MathUtils 8import utility.{HasCircularQueuePtrHelper, XSError} 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Bundles.NumLsElem 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16 17object EntryBundles extends HasCircularQueuePtrHelper { 18 19 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 20 //basic status 21 val robIdx = new RobPtr 22 val fuType = IQFuType() 23 //src status 24 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 25 //issue status 26 val blocked = Bool() 27 val issued = Bool() 28 val firstIssue = Bool() 29 val issueTimer = UInt(2.W) 30 val deqPortIdx = UInt(1.W) 31 //vector mem status 32 val vecMem = Option.when(params.isVecMemIQ)(new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 55 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(ExuVec()) 56 //reg cache 57 val useRegCache = Option.when(params.needReadRegCache)(Bool()) 58 val regCacheIdx = Option.when(params.needReadRegCache)(UInt(RegCacheIdxWidth.W)) 59 } 60 61 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 62 val sqIdx = new SqPtr 63 val lqIdx = new LqPtr 64 val numLsElem = NumLsElem() 65 } 66 67 class EntryDeqRespBundle(implicit p: Parameters, val params: IssueBlockParams) extends XSBundle { 68 val robIdx = new RobPtr 69 val resp = RespType() 70 val fuType = FuType() 71 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 72 val sqIdx = Option.when(params.needFeedBackSqIdx)(new SqPtr()) 73 val lqIdx = Option.when(params.needFeedBackLqIdx)(new LqPtr()) 74 } 75 76 object RespType { 77 def apply() = UInt(2.W) 78 79 def isBlocked(resp: UInt) = { 80 resp === block 81 } 82 83 def succeed(resp: UInt) = { 84 resp === success 85 } 86 87 val block = "b00".U 88 val uncertain = "b01".U 89 val success = "b11".U 90 } 91 92 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 93 val status = new Status() 94 val imm = Option.when(params.needImm)(UInt((params.deqImmTypesMaxLen).W)) 95 val payload = new DynInst() 96 } 97 98 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 99 val flush = Flipped(ValidIO(new Redirect)) 100 val enq = Flipped(ValidIO(new EntryBundle)) 101 //wakeup 102 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 103 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 104 // vl 105 val vlFromIntIsZero = Input(Bool()) 106 val vlFromIntIsVlmax = Input(Bool()) 107 val vlFromVfIsZero = Input(Bool()) 108 val vlFromVfIsVlmax = Input(Bool()) 109 //cancel 110 val og0Cancel = Input(ExuVec()) 111 val og1Cancel = Input(ExuVec()) 112 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 113 //deq sel 114 val deqSel = Input(Bool()) 115 val deqPortIdxWrite = Input(UInt(1.W)) 116 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 117 //trans sel 118 val transSel = Input(Bool()) 119 // vector mem only 120 val fromLsq = Option.when(params.isVecMemIQ)(new Bundle { 121 val sqDeqPtr = Input(new SqPtr) 122 val lqDeqPtr = Input(new LqPtr) 123 }) 124 } 125 126 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 127 //status 128 val valid = Output(Bool()) 129 val issued = Output(Bool()) 130 val canIssue = Output(Bool()) 131 val fuType = Output(FuType()) 132 val robIdx = Output(new RobPtr) 133 val uopIdx = Option.when(params.isVecMemIQ)(Output(UopIdx())) 134 //src 135 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 136 val srcWakeUpL1ExuOH = Option.when(params.hasIQWakeUp)(Vec(params.numRegSrc, Output(ExuVec()))) 137 //deq 138 val isFirstIssue = Output(Bool()) 139 val entry = ValidIO(new EntryBundle) 140 val cancelBypass = Output(Bool()) 141 val deqPortIdxRead = Output(UInt(1.W)) 142 val issueTimerRead = Output(UInt(2.W)) 143 //trans 144 val enqReady = Output(Bool()) 145 val transEntry = ValidIO(new EntryBundle) 146 // debug 147 val entryInValid = Output(Bool()) 148 val entryOutDeqValid = Output(Bool()) 149 val entryOutTransValid = Output(Bool()) 150 val perfLdCancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 151 val perfOg0Cancel = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Bool()))) 152 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 153 val perfWakeupByIQ = Option.when(params.hasIQWakeUp)(Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 154 } 155 156 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 157 val validRegNext = Bool() 158 val flushed = Bool() 159 val clear = Bool() 160 val canIssue = Bool() 161 val enqReady = Bool() 162 val deqSuccess = Bool() 163 val srcWakeup = Vec(params.numRegSrc, Bool()) 164 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 165 val vlWakeupByIntWb = Bool() 166 val vlWakeupByVfWb = Bool() 167 val srcCancelVec = Vec(params.numRegSrc, Bool()) 168 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 169 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 170 } 171 172 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 173 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 174 common.flushed := status.robIdx.needFlush(commonIn.flush) 175 common.deqSuccess := (if (params.isVecMemIQ) status.issued else true.B) && 176 commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 177 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 178 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 179 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 180 if (params.numRegSrc == 5) { 181 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 182 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 183 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 184 } 185 else 186 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 187 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 188 common.canIssue := validReg && status.canIssue 189 common.enqReady := !validReg || commonIn.transSel 190 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 191 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 192 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 193 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 194 srcCancel := srcLoadCancel || ldTransCancel 195 } 196 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 197 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 198 } 199 if(isEnq) { 200 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 201 } else { 202 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 203 } 204 if (params.numRegSrc == 5) { 205 // only when numRegSrc == 5 need vl 206 val wakeUpFromVl = VecInit(commonIn.wakeUpFromWB.map{ bundle => 207 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 208 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 209 }) 210 var numVecWb = params.backendParam.getVfWBExeGroup.size 211 var numV0Wb = params.backendParam.getV0WBExeGroup.size 212 // int wb is first bit of vlwb, which is after vfwb and v0wb 213 common.vlWakeupByIntWb := wakeUpFromVl(numVecWb + numV0Wb) 214 // vf wb is second bit of wb 215 common.vlWakeupByVfWb := wakeUpFromVl(numVecWb + numV0Wb + 1) 216 } else { 217 common.vlWakeupByIntWb := false.B 218 common.vlWakeupByVfWb := false.B 219 } 220 } 221 222 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 223 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 224 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 225 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 226 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 227 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 228 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 229 val canIssueBypass = Bool() 230 } 231 232 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 233 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 234 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 235 if (params.numRegSrc == 5) { 236 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 237 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 238 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 239 } 240 else 241 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 242 }.toSeq.transpose 243 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 244 245 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 246 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 247 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 248 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 249 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 250 case (exuOH, regExuOH) => 251 exuOH := 0.U.asTypeOf(exuOH) 252 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 253 } 254 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 255 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 256 wakeupVec.asUInt.orR | state 257 }).asUInt.andR 258 } 259 260 261 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 262 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 263 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 264 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 265 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 266 case ((dep, originalDep), deqPortIdx) => 267 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 268 dep := 1.U 269 else 270 dep := originalDep << 1 271 } 272 } 273 } 274 275 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 276 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 277 OH.zip(allExuParams).map{case (oh,e) => 278 if (e.isVfExeUnit) oh else false.B 279 }.reduce(_ || _) 280 } 281 282 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 283 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 284 val cancelByLd = common.srcCancelVec.asUInt.orR 285 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 286 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 287 entryUpdate.status.robIdx := status.robIdx 288 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 289 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 290 val cancel = common.srcCancelVec(srcIdx) 291 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 292 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 293 val wakeup = common.srcWakeup(srcIdx) 294 295 val ignoreOldVd = Wire(Bool()) 296 val vlWakeUpByIntWb = common.vlWakeupByIntWb 297 val vlWakeUpByVfWb = common.vlWakeupByVfWb 298 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 299 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 300 val vta = entryReg.payload.vpu.vta 301 val vma = entryReg.payload.vpu.vma 302 val vm = entryReg.payload.vpu.vm 303 val vlFromIntIsZero = commonIn.vlFromIntIsZero 304 val vlFromIntIsVlmax = commonIn.vlFromIntIsVlmax 305 val vlFromVfIsZero = commonIn.vlFromVfIsZero 306 val vlFromVfIsVlmax = commonIn.vlFromVfIsVlmax 307 val vlIsVlmax = (vlFromIntIsVlmax && vlWakeUpByIntWb) || (vlFromVfIsVlmax && vlWakeUpByVfWb) 308 val vlIsNonZero = (!vlFromIntIsZero && vlWakeUpByIntWb) || (!vlFromVfIsZero && vlWakeUpByVfWb) 309 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 310 val ignoreWhole = (vm =/= 0.U || vma) && vta 311 val srcIsVec = SrcType.isVp(srcStatus.srcType) 312 if (params.numVfSrc > 0 && srcIdx == 2) { 313 /** 314 * the src store the old vd, update it when vl is write back 315 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 316 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 317 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 318 */ 319 ignoreOldVd := !VlduType.isFof(entryReg.payload.fuOpType) && srcIsVec && vlIsNonZero && !isDependOldvd && (ignoreTail || ignoreWhole) 320 } else { 321 ignoreOldVd := false.B 322 } 323 324 srcStatusNext.psrc := srcStatus.psrc 325 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 326 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 327 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 328 // Vf / Mem -> Vf 329 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 330 MuxCase(srcStatus.dataSources.value, Seq( 331 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 332 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 333 srcStatus.dataSources.readBypass -> DataSource.bypass2, 334 srcStatus.dataSources.readBypass2 -> DataSource.reg, 335 )) 336 } 337 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 338 // Vf / Int -> Mem 339 MuxCase(srcStatus.dataSources.value, Seq( 340 wakeupByIQ -> DataSource.bypass, 341 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 342 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 343 srcStatus.dataSources.readBypass2 -> DataSource.reg, 344 )) 345 } 346 else { 347 MuxCase(srcStatus.dataSources.value, Seq( 348 wakeupByIQ -> DataSource.bypass, 349 srcStatus.dataSources.readBypass -> DataSource.reg, 350 )) 351 }) 352 if(params.hasIQWakeUp) { 353 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 354 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 355 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 356 common.srcLoadDependencyNext(srcIdx)) 357 } else { 358 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 359 } 360 361 if (params.needReadRegCache) { 362 val wakeupSrcExuWriteRC = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.needWriteRegCache) 363 val wakeupRC = wakeupSrcExuWriteRC.map(_._1).fold(false.B)(_ || _) && SrcType.isXp(srcStatus.srcType) 364 val wakeupRCIdx = Mux1H(wakeupSrcExuWriteRC.map(_._1), wakeupSrcExuWriteRC.map(_._2.bits.rcDest.get)) 365 val replaceRC = wakeupSrcExuWriteRC.map(x => x._2.bits.rfWen && x._2.bits.rcDest.get === srcStatus.regCacheIdx.get).fold(false.B)(_ || _) 366 367 srcStatusNext.useRegCache.get := MuxCase(srcStatus.useRegCache.get, Seq( 368 cancel -> false.B, 369 wakeupRC -> true.B, 370 replaceRC -> false.B, 371 )) 372 srcStatusNext.regCacheIdx.get := Mux(wakeupRC, wakeupRCIdx, srcStatus.regCacheIdx.get) 373 } 374 } 375 entryUpdate.status.blocked := false.B 376 entryUpdate.status.issued := MuxCase(status.issued, Seq( 377 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 378 commonIn.deqSel -> true.B, 379 !status.srcReady -> false.B, 380 )) 381 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 382 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 383 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 384 entryUpdate.imm.foreach(_ := entryReg.imm.get) 385 entryUpdate.payload := entryReg.payload 386 if (params.isVecMemIQ) { 387 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 388 } 389 } 390 391 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 392 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 393 commonOut.valid := validReg 394 commonOut.issued := entryReg.status.issued 395 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 396 else common.canIssue && !common.flushed) 397 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 398 commonOut.robIdx := status.robIdx 399 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 400 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 401 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 402 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 403 val useRegCache = status.srcStatus(srcIdx).useRegCache.getOrElse(false.B) && status.srcStatus(srcIdx).dataSources.readReg 404 dataSourceOut.value := (if (isComp) 405 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 406 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 407 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 408 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 409 )) 410 } else { 411 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 412 wakeupByIQWithoutCancel -> DataSource.forward, 413 useRegCache -> DataSource.regcache, 414 )) 415 } 416 else { 417 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 418 useRegCache -> DataSource.regcache, 419 )) 420 }) 421 } 422 commonOut.isFirstIssue := !status.firstIssue 423 commonOut.entry.valid := validReg 424 commonOut.entry.bits := entryReg 425 if(isEnq) { 426 commonOut.entry.bits.status := status 427 } 428 commonOut.issueTimerRead := status.issueTimer 429 commonOut.deqPortIdxRead := status.deqPortIdx 430 431 if(params.hasIQWakeUp) { 432 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 433 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 434 if (isComp) 435 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 436 else 437 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 438 } 439 } 440 441 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 442 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 443 if(params.hasIQWakeUp) { 444 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 445 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 446 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 447 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 448 wakeupSrcLoadDependency(srcIdx), 449 status.srcStatus(srcIdx).srcLoadDependency) 450 else status.srcStatus(srcIdx).srcLoadDependency) 451 } 452 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 453 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 454 wakeupSrcLoadDependencyNext(srcIdx), 455 common.srcLoadDependencyNext(srcIdx)) 456 else common.srcLoadDependencyNext(srcIdx)) 457 } 458 } else { 459 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 460 srcLoadDependencyOut := common.srcLoadDependencyNext 461 } 462 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 463 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 464 ldOut := srcLoadDependencyOut(srcIdx) 465 } 466 467 commonOut.enqReady := common.enqReady 468 commonOut.transEntry.valid := validReg && !common.flushed && !status.issued 469 commonOut.transEntry.bits := entryUpdate 470 // debug 471 commonOut.entryInValid := commonIn.enq.valid 472 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 473 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 474 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 475 if (params.hasIQWakeUp) { 476 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 477 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 478 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 479 } 480 // vecMem 481 if (params.isVecMemIQ) { 482 commonOut.uopIdx.get := entryReg.payload.uopIdx 483 } 484 } 485 486 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 487 val fromLsq = commonIn.fromLsq.get 488 val vecMemStatus = entryReg.status.vecMem.get 489 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 490 vecMemStatusUpdate := vecMemStatus 491 492 val isFirstLoad = entryReg.status.vecMem.get.lqIdx === fromLsq.lqDeqPtr 493 494 val isVleff = entryReg.payload.vpu.isVleff 495 // update blocked 496 entryUpdate.status.blocked := !isFirstLoad && isVleff 497 } 498 499 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 500 val origExuOH = Wire(chiselTypeOf(exuOH)) 501 when(wakeupByIQOH.asUInt.orR) { 502 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 503 }.otherwise { 504 origExuOH := regSrcExuOH 505 } 506 exuOH := 0.U.asTypeOf(exuOH) 507 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 508 } 509 510 object IQFuType { 511 def num = FuType.num 512 513 def apply() = Vec(num, Bool()) 514 515 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 516 val res = WireDefault(0.U.asTypeOf(fuType)) 517 fus.foreach(x => res(x.id) := fuType(x.id)) 518 res 519 } 520 } 521 522 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 523 //wakeup 524 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 525 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 526 //cancel 527 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 528 val og0Cancel = Input(ExuVec()) 529 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 530 } 531 532 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 533 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 534 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 535 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 536 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 537 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 538 } 539 540 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 541 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 542 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 543 if (i == 3) 544 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 545 else if (i == 4) 546 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 547 else 548 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 549 }.reduce(_ || _) 550 } 551 552 if (params.hasIQWakeUp) { 553 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 554 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 555 if (params.numRegSrc == 5) { 556 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 557 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 558 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 559 } 560 else 561 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 562 }.toIndexedSeq.transpose 563 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 564 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 565 } else { 566 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 567 } 568 569 if (params.hasIQWakeUp) { 570 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 571 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 572 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 573 } 574 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 575 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 576 } 577 } else { 578 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 579 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 580 } 581 582 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 583 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 584 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 585 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 586 dp := 1.U << (delay - 1) 587 else 588 dp := ldp << delay 589 } 590 } 591 } 592} 593