1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utility.ZeroExt 6import xiangshan.VSETOpType 7import xiangshan.backend.decode.Imm_VSETIVLI 8import xiangshan.backend.decode.isa.bitfield.InstVType 9import xiangshan.backend.fu.vector.Bundles.VType 10import xiangshan.backend.fu.{FuConfig, FuncUnit, PipedFuncUnit, VsetModule, VtypeStruct} 11import xiangshan.backend.fu.vector.Bundles.VConfig 12 13class VSetBase(cfg: FuConfig)(implicit p: Parameters) extends PipedFuncUnit(cfg) { 14 val debugIO = IO(new Bundle() { 15 val vconfig = Output(VConfig()) 16 }) 17 protected val in = io.in.bits 18 protected val out = io.out.bits 19 20 protected val vsetModule = Module(new VsetModule) 21 22 protected val flushed = io.in.bits.ctrl.robIdx.needFlush(io.flush) 23 24 protected val avlImm = Imm_VSETIVLI().getAvl(in.data.src(1)) 25 protected val avl = Mux(VSETOpType.isVsetivli(in.ctrl.fuOpType), avlImm, in.data.src(0)) 26 27 protected val instVType: InstVType = Imm_VSETIVLI().getVType(in.data.src(1)) 28 protected val vtypeImm: VType = VType.fromInstVType(instVType) 29 protected val vtype: VType = Mux(VSETOpType.isVsetvl(in.ctrl.fuOpType), VType.fromVtypeStruct(in.data.src(1).asTypeOf(new VtypeStruct())), vtypeImm) 30 31 vsetModule.io.in.func := in.ctrl.fuOpType 32 33 io.out.valid := io.in.valid 34 io.in.ready := io.out.ready 35} 36 37 38/** 39 * Wrapper of VsetModule 40 * This fu is uop of vset which reads two int regs and writes one int regs.<br> 41 * uop: <br/> 42 * [[VSETOpType.uvsetrd_ii]], <br/> 43 * [[VSETOpType.uvsetrd_xi]], <br/> 44 * [[VSETOpType.uvsetrd_xx]], <br/> 45 * [[VSETOpType.uvsetrd_vlmax_i]], <br/> 46 * [[VSETOpType.uvsetrd_vlmax_x]], <br/> 47 * @param cfg [[FuConfig]] 48 * @param p [[Parameters]] 49 */ 50class VSetRiWi(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) { 51 vsetModule.io.in.avl := avl 52 vsetModule.io.in.vtype := vtype 53 54 out.res.data := vsetModule.io.out.vconfig.vl 55 56 debugIO.vconfig := vsetModule.io.out.vconfig 57} 58 59/** 60 * Wrapper of VsetModule 61 * This fu is uop of vset which reads two int regs and writes one vf regs.<br> 62 * uop: <br/> 63 * [[VSETOpType.uvsetvcfg_ii]], <br/> 64 * [[VSETOpType.uvsetvcfg_xi]], <br/> 65 * [[VSETOpType.uvsetvcfg_xx]], <br/> 66 * [[VSETOpType.uvsetvcfg_vlmax_i]], <br/> 67 * [[VSETOpType.uvsetvcfg_vlmax_x]], <br/> 68 * @param cfg [[FuConfig]] 69 * @param p [[Parameters]] 70 */ 71class VSetRiWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) { 72 vsetModule.io.in.avl := avl 73 vsetModule.io.in.vtype := vtype 74 val vl = vsetModule.io.out.vconfig.vl 75 val vlmax = vsetModule.io.out.vlmax 76 77 out.res.data := ZeroExt(vsetModule.io.out.vconfig.asUInt, XLEN) 78 79 if (cfg.writeVConfig) io.vlIsZero.get := vl === 0.U 80 if (cfg.writeVConfig) io.vlIsVlmax.get := vl === vlmax 81 82 debugIO.vconfig := vsetModule.io.out.vconfig 83} 84 85/** 86 * Wrapper of VsetModule 87 * This fu is uop of vset which reads two int regs and writes one vf regs.<br> 88 * uop: <br/> 89 * [[VSETOpType.uvsetvcfg_vv]], <br/> 90 * [[VSETOpType.uvsetvcfg_keep_v]], <br/> 91 * @param cfg [[FuConfig]] 92 * @param p [[Parameters]] 93 */ 94class VSetRvfWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) { 95 vsetModule.io.in.avl := 0.U 96 vsetModule.io.in.vtype := vtype 97 98 val oldVL = in.data.src(0).asTypeOf(VConfig()).vl 99 val res = WireInit(0.U.asTypeOf(VConfig())) 100 val vlmax = vsetModule.io.out.vlmax 101 res.vl := Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U, 102 Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), oldVL, vsetModule.io.out.vconfig.vl)) 103 res.vtype := vsetModule.io.out.vconfig.vtype 104 105 out.res.data := ZeroExt(res.asUInt, XLEN) 106 107 if (cfg.writeVConfig) io.vlIsZero.get := res.vl === 0.U 108 if (cfg.writeVConfig) io.vlIsVlmax.get := res.vl === vlmax 109 110 debugIO.vconfig := res 111} 112