xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala (revision a32c56f428c85705bf274a3011ddbec711d929d9) 
1package xiangshan.backend.fu.wrapper
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import utility.ZeroExt
6import xiangshan.VSETOpType
7import xiangshan.backend.decode.Imm_VSETIVLI
8import xiangshan.backend.decode.isa.bitfield.InstVType
9import xiangshan.backend.fu.vector.Bundles.VType
10import xiangshan.backend.fu.{FuConfig, FuncUnit, VsetModule}
11
12class VSetBase(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) {
13  protected val in = io.in.bits
14  protected val out = io.out.bits
15
16  protected val vsetModule = Module(new VsetModule)
17
18  protected val flushed = io.in.bits.robIdx.needFlush(io.flush)
19
20  protected val avlImm = Imm_VSETIVLI().getAvl(in.src(1))
21  protected val avl = Mux(VSETOpType.isVsetivli(in.fuOpType), avlImm, in.src(0))
22
23  protected val instVType: InstVType = Imm_VSETIVLI().getVType(in.src(1))
24  protected val vtypeImm: VType = VType.fromInstVType(instVType)
25  protected val vtype: VType = Mux(VSETOpType.isVsetvl(in.fuOpType), in.src(1)(7, 0).asTypeOf(new VType), vtypeImm)
26
27  vsetModule.io.in.func := in.fuOpType
28
29  io.out.valid := io.in.valid
30  io.in.ready := io.out.ready
31}
32
33
34/**
35  * Wrapper of VsetModule
36  * This fu is uop of vset which reads two int regs and writes one int regs.<br>
37  * uop: <br/>
38  * [[VSETOpType.uvsetrd_ii]], <br/>
39  * [[VSETOpType.uvsetrd_xi]], <br/>
40  * [[VSETOpType.uvsetrd_xx]], <br/>
41  * [[VSETOpType.uvsetrd_vlmax_i]], <br/>
42  * [[VSETOpType.uvsetrd_vlmax_x]], <br/>
43  * @param cfg [[FuConfig]]
44  * @param p [[Parameters]]
45  */
46class VSetIVL(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
47  vsetModule.io.in.avl := avl
48  vsetModule.io.in.vtype := vtype
49  vsetModule.io.in.oldVl := 0.U
50
51  out.data := vsetModule.io.out.vconfig.vl
52
53  connectNonPipedCtrlSingal
54}
55
56/**
57  * Wrapper of VsetModule
58  * This fu is uop of vset which reads two int regs and writes one vf regs.<br>
59  * uop: <br/>
60  * [[VSETOpType.uvsetvcfg_ii]], <br/>
61  * [[VSETOpType.uvsetvcfg_xi]], <br/>
62  * [[VSETOpType.uvsetvcfg_xx]], <br/>
63  * [[VSETOpType.uvsetvcfg_vlmax_i]], <br/>
64  * [[VSETOpType.uvsetvcfg_vlmax_x]], <br/>
65  * @param cfg [[FuConfig]]
66  * @param p [[Parameters]]
67  */
68class VSetIVConfig(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
69  vsetModule.io.in.avl := avl
70  vsetModule.io.in.vtype := vtype
71  vsetModule.io.in.oldVl := 0.U
72
73  out.data := ZeroExt(vsetModule.io.out.vconfig.asUInt, XLEN)
74
75  connectNonPipedCtrlSingal
76}
77
78/**
79  * Wrapper of VsetModule
80  * This fu is uop of vset which reads two int regs and writes one vf regs.<br>
81  * uop: <br/>
82  * [[VSETOpType.uvsetvcfg_vv]], <br/>
83  * [[VSETOpType.uvsetvcfg_keep_v]], <br/>
84  * @param cfg [[FuConfig]]
85  * @param p [[Parameters]]
86  */
87class VSetFVConfig(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
88  vsetModule.io.in.avl := 0.U
89  vsetModule.io.in.vtype := vtype
90  vsetModule.io.in.oldVl := in.src(0)
91
92  out.data := ZeroExt(vsetModule.io.out.vconfig.asUInt, XLEN)
93
94  connectNonPipedCtrlSingal
95}
96