xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala (revision 887862dbb8debde8ab099befc426493834a69ee7) 
1package xiangshan.backend.fu.wrapper
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import utility.ZeroExt
6import xiangshan.{VSETOpType, CSROpType}
7import xiangshan.backend.decode.{Imm_VSETIVLI, Imm_VSETVLI}
8import xiangshan.backend.decode.isa.bitfield.InstVType
9import xiangshan.backend.fu.vector.Bundles.VsetVType
10import xiangshan.backend.fu.{FuConfig, FuncUnit, PipedFuncUnit, VsetModule, VtypeStruct}
11import xiangshan.backend.fu.vector.Bundles.VConfig
12
13class VSetBase(cfg: FuConfig)(implicit p: Parameters) extends PipedFuncUnit(cfg) {
14  val debugIO = IO(new Bundle() {
15    val vconfig = Output(VConfig())
16  })
17  protected val in = io.in.bits
18  protected val out = io.out.bits
19
20  protected val vsetModule = Module(new VsetModule)
21
22  protected val flushed = io.in.bits.ctrl.robIdx.needFlush(io.flush)
23
24  protected val avlImm = Imm_VSETIVLI().getAvl(in.data.src(1))
25  protected val avl = Mux(VSETOpType.isVsetivli(in.ctrl.fuOpType), avlImm, in.data.src(0))
26
27  protected val instVType: InstVType = Mux(VSETOpType.isVsetivli(in.ctrl.fuOpType), Imm_VSETIVLI().getVType(in.data.src(1)), Imm_VSETVLI().getVType(in.data.src(1)))
28  protected val vtypeImm: VsetVType = VsetVType.fromInstVType(instVType)
29  protected val vtype: VsetVType = Mux(VSETOpType.isVsetvl(in.ctrl.fuOpType), VsetVType.fromVtypeStruct(in.data.src(1).asTypeOf(new VtypeStruct())), vtypeImm)
30
31  vsetModule.io.in.func := in.ctrl.fuOpType
32  connect0LatencyCtrlSingal
33  io.out.valid := io.in.valid
34  io.in.ready := io.out.ready
35}
36
37
38/**
39  * Wrapper of VsetModule
40  * This fu is uop of vset which reads two int regs and writes one int regs.<br>
41  * uop: <br/>
42  * [[VSETOpType.uvsetrd_ii]], <br/>
43  * [[VSETOpType.uvsetrd_xi]], <br/>
44  * [[VSETOpType.uvsetrd_xx]], <br/>
45  * [[VSETOpType.uvsetrd_vlmax_i]], <br/>
46  * [[VSETOpType.uvsetrd_vlmax_x]], <br/>
47  * @param cfg [[FuConfig]]
48  * @param p [[Parameters]]
49  */
50class VSetRiWi(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
51  vsetModule.io.in.avl := avl
52  vsetModule.io.in.vtype := vtype
53
54  out.res.data := vsetModule.io.out.vconfig.vl
55
56  debugIO.vconfig := vsetModule.io.out.vconfig
57}
58
59/**
60  * Wrapper of VsetModule
61  * This fu is uop of vset which reads two int regs and writes one vf regs.<br>
62  * uop: <br/>
63  * [[VSETOpType.uvsetvcfg_ii]], <br/>
64  * [[VSETOpType.uvsetvcfg_xi]], <br/>
65  * [[VSETOpType.uvsetvcfg_xx]], <br/>
66  * [[VSETOpType.uvsetvcfg_vlmax_i]], <br/>
67  * [[VSETOpType.uvsetvcfg_vlmax_x]], <br/>
68  * @param cfg [[FuConfig]]
69  * @param p [[Parameters]]
70  */
71class VSetRiWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
72  vsetModule.io.in.avl := avl
73  vsetModule.io.in.vtype := vtype
74  val vl = vsetModule.io.out.vconfig.vl
75  val vlmax = vsetModule.io.out.vlmax
76  val isVsetvl = VSETOpType.isVsetvl(in.ctrl.fuOpType)
77
78  out.res.data := vsetModule.io.out.vconfig.vl
79
80  if (cfg.writeVlRf) io.vtype.get.bits := vsetModule.io.out.vconfig.vtype
81  if (cfg.writeVlRf) io.vtype.get.valid := io.out.valid && isVsetvl
82  if (cfg.writeVlRf) io.vlIsZero.get := vl === 0.U
83  if (cfg.writeVlRf) io.vlIsVlmax.get := vl === vlmax
84
85  debugIO.vconfig := vsetModule.io.out.vconfig
86}
87
88/**
89  * Wrapper of VsetModule
90  * This fu is uop of vset which reads two int regs and writes one vf regs.<br>
91  * uop: <br/>
92  * [[VSETOpType.uvsetvcfg_vv]], <br/>
93  * [[VSETOpType.uvsetvcfg_keep_v]], <br/>
94  * @param cfg [[FuConfig]]
95  * @param p [[Parameters]]
96  */
97class VSetRvfWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
98  vsetModule.io.in.avl := 0.U
99  vsetModule.io.in.vtype := vtype
100
101  val oldVL = in.data.src(4).asTypeOf(VConfig()).vl
102  val res = WireInit(0.U.asTypeOf(VConfig()))
103  val vlmax = vsetModule.io.out.vlmax
104  val isVsetvl = VSETOpType.isVsetvl(in.ctrl.fuOpType)
105  val isReadVl = in.ctrl.fuOpType === VSETOpType.csrrvl
106  res.vl := Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U,
107              Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), oldVL, vsetModule.io.out.vconfig.vl))
108  res.vtype := vsetModule.io.out.vconfig.vtype
109
110  out.res.data := Mux(isReadVl, oldVL,
111                    Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U,
112                      Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType),
113                        Mux(oldVL < vlmax, oldVL, vlmax), vsetModule.io.out.vconfig.vl)))
114
115  if (cfg.writeVlRf) io.vtype.get.bits := vsetModule.io.out.vconfig.vtype
116  if (cfg.writeVlRf) io.vtype.get.valid := isVsetvl && io.out.valid
117  if (cfg.writeVlRf) io.vlIsZero.get := !isReadVl && res.vl === 0.U
118  if (cfg.writeVlRf) io.vlIsVlmax.get := !isReadVl && res.vl === vlmax
119
120  debugIO.vconfig := res
121}
122