xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala (revision 6a35d972887e2dbfc0705b0fa8b979b13df0f3d1) 
1package xiangshan.backend.fu.wrapper
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import utility.ZeroExt
6import xiangshan.VSETOpType
7import xiangshan.backend.decode.Imm_VSETIVLI
8import xiangshan.backend.decode.isa.bitfield.InstVType
9import xiangshan.backend.fu.vector.Bundles.VType
10import xiangshan.backend.fu.{FuConfig, FuncUnit, VsetModule, VtypeStruct}
11import xiangshan.backend.fu.vector.Bundles.VConfig
12
13class VSetBase(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) {
14  val debugIO = IO(new Bundle() {
15    val vconfig = Output(VConfig())
16  })
17  protected val in = io.in.bits
18  protected val out = io.out.bits
19
20  protected val vsetModule = Module(new VsetModule)
21
22  protected val flushed = io.in.bits.ctrl.robIdx.needFlush(io.flush)
23
24  protected val avlImm = Imm_VSETIVLI().getAvl(in.data.src(1))
25  protected val avl = Mux(VSETOpType.isVsetivli(in.ctrl.fuOpType), avlImm, in.data.src(0))
26
27  protected val instVType: InstVType = Imm_VSETIVLI().getVType(in.data.src(1))
28  protected val vtypeImm: VType = VType.fromInstVType(instVType)
29  protected val vtype: VType = Mux(VSETOpType.isVsetvl(in.ctrl.fuOpType), VType.fromVtypeStruct(in.data.src(1).asTypeOf(new VtypeStruct())), vtypeImm)
30
31  vsetModule.io.in.func := in.ctrl.fuOpType
32
33  io.out.valid := io.in.valid
34  io.in.ready := io.out.ready
35}
36
37
38/**
39  * Wrapper of VsetModule
40  * This fu is uop of vset which reads two int regs and writes one int regs.<br>
41  * uop: <br/>
42  * [[VSETOpType.uvsetrd_ii]], <br/>
43  * [[VSETOpType.uvsetrd_xi]], <br/>
44  * [[VSETOpType.uvsetrd_xx]], <br/>
45  * [[VSETOpType.uvsetrd_vlmax_i]], <br/>
46  * [[VSETOpType.uvsetrd_vlmax_x]], <br/>
47  * @param cfg [[FuConfig]]
48  * @param p [[Parameters]]
49  */
50class VSetRiWi(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
51  vsetModule.io.in.avl := avl
52  vsetModule.io.in.vtype := vtype
53
54  out.res.data := vsetModule.io.out.vconfig.vl
55
56  connectNonPipedCtrlSingal
57
58  debugIO.vconfig := vsetModule.io.out.vconfig
59}
60
61/**
62  * Wrapper of VsetModule
63  * This fu is uop of vset which reads two int regs and writes one vf regs.<br>
64  * uop: <br/>
65  * [[VSETOpType.uvsetvcfg_ii]], <br/>
66  * [[VSETOpType.uvsetvcfg_xi]], <br/>
67  * [[VSETOpType.uvsetvcfg_xx]], <br/>
68  * [[VSETOpType.uvsetvcfg_vlmax_i]], <br/>
69  * [[VSETOpType.uvsetvcfg_vlmax_x]], <br/>
70  * @param cfg [[FuConfig]]
71  * @param p [[Parameters]]
72  */
73class VSetRiWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
74  vsetModule.io.in.avl := avl
75  vsetModule.io.in.vtype := vtype
76
77  out.res.data := ZeroExt(vsetModule.io.out.vconfig.asUInt, XLEN)
78
79  connectNonPipedCtrlSingal
80
81  debugIO.vconfig := vsetModule.io.out.vconfig
82}
83
84/**
85  * Wrapper of VsetModule
86  * This fu is uop of vset which reads two int regs and writes one vf regs.<br>
87  * uop: <br/>
88  * [[VSETOpType.uvsetvcfg_vv]], <br/>
89  * [[VSETOpType.uvsetvcfg_keep_v]], <br/>
90  * @param cfg [[FuConfig]]
91  * @param p [[Parameters]]
92  */
93class VSetRvfWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
94  vsetModule.io.in.avl := 0.U
95  vsetModule.io.in.vtype := vtype
96
97  val oldVL = in.data.src(0).asTypeOf(VConfig()).vl
98  val res = WireInit(0.U.asTypeOf(VConfig()))
99  res.vl := Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U,
100              Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), oldVL, vsetModule.io.out.vconfig.vl))
101  res.vtype := vsetModule.io.out.vconfig.vtype
102
103  out.res.data := ZeroExt(res.asUInt, XLEN)
104
105  connectNonPipedCtrlSingal
106
107  debugIO.vconfig := res
108}
109