xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala (revision e1d5ffc2d93873b72146e78c8f6a904926de8590) 
1package xiangshan.backend.fu.wrapper
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.decode._
7import utility.XSError
8import xiangshan.backend.fu.FuConfig
9import xiangshan.backend.fu.vector.{Mgu, VecPipedFuncUnit}
10import xiangshan.ExceptionNO
11import xiangshan.FuOpType
12import yunsuan.VfpuType
13import yunsuan.vector.VectorConvert.VectorCvt
14import yunsuan.util._
15
16
17class VCVT(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) {
18  XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfcvt OpType not supported")
19
20  // params alias
21  private val dataWidth = cfg.destDataBits
22  private val dataWidthOfDataModule = 64
23  private val numVecModule = dataWidth / dataWidthOfDataModule
24
25  // io alias
26  private val opcode = fuOpType(8, 0)
27  private val sew = vsew
28
29  private val isRtz = opcode(2) & opcode(1)
30  private val isRod = opcode(2) & !opcode(1) & opcode(0)
31  private val isFrm = !isRtz && !isRod
32  private val vfcvtRm = Mux1H(
33    Seq(isRtz, isRod, isFrm),
34    Seq(1.U, 6.U, rm)
35  )
36
37  private val lmul = vlmul // -3->3 => 1/8 ->8
38
39  val widen = opcode(4, 3) // 0->single 1->widen 2->norrow => width of result
40  val isSingleCvt = !widen(1) & !widen(0)
41  val isWidenCvt = !widen(1) & widen(0)
42  val isNarrowCvt = widen(1) & !widen(0)
43  val fire = io.in.valid
44  val fireReg = GatedValidRegNext(fire)
45
46  // output width 8， 16， 32， 64
47  val output1H = Wire(UInt(4.W))
48  output1H := chisel3.util.experimental.decode.decoder(
49    widen ## sew,
50    TruthTable(
51      Seq(
52        BitPat("b00_01") -> BitPat("b0010"), // 16
53        BitPat("b00_10") -> BitPat("b0100"), // 32
54        BitPat("b00_11") -> BitPat("b1000"), // 64
55
56        BitPat("b01_00") -> BitPat("b0010"), // 16
57        BitPat("b01_01") -> BitPat("b0100"), // 32
58        BitPat("b01_10") -> BitPat("b1000"), // 64
59
60        BitPat("b10_00") -> BitPat("b0001"), // 8
61        BitPat("b10_01") -> BitPat("b0010"), // 16
62        BitPat("b10_10") -> BitPat("b0100"), // 32
63      ),
64      BitPat.N(4)
65    )
66  )
67  if(backendParams.debugEn) {
68    dontTouch(output1H)
69  }
70  val outputWidth1H = output1H
71  val outIs32bits = RegNext(RegNext(outputWidth1H(2)))
72  val outIsInt = !outCtrl.fuOpType(6)
73  val outIsMvInst = outCtrl.fuOpType === FuOpType.FMVXF
74
75  val outEew = RegEnable(RegEnable(Mux1H(output1H, Seq(0,1,2,3).map(i => i.U)), fire), fireReg)
76  private val needNoMask = outVecCtrl.fpu.isFpToVecInst
77  val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask)
78
79  // modules
80  private val vfcvt = Module(new VectorCvtTop(dataWidth, dataWidthOfDataModule))
81  private val mgu = Module(new Mgu(dataWidth))
82
83  val vs2Vec = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W)))
84  vs2Vec := vs2.asTypeOf(vs2Vec)
85
86  /**
87   * [[vfcvt]]'s in connection
88   */
89  vfcvt.uopIdx := vuopIdx(0)
90  vfcvt.src := vs2Vec
91  vfcvt.opType := opcode(7,0)
92  vfcvt.sew := sew
93  vfcvt.rm := vfcvtRm
94  vfcvt.outputWidth1H := outputWidth1H
95  vfcvt.isWiden := isWidenCvt
96  vfcvt.isNarrow := isNarrowCvt
97  vfcvt.fire := fire
98  vfcvt.isFpToVecInst := vecCtrl.fpu.isFpToVecInst
99  val vfcvtResult = vfcvt.io.result
100  val vfcvtFflags = vfcvt.io.fflags
101
102  /** fflags:
103   */
104  val eNum1H = chisel3.util.experimental.decode.decoder(sew ## (isWidenCvt || isNarrowCvt),
105    TruthTable(
106      Seq(                     // 8, 4, 2, 1
107        BitPat("b001") -> BitPat("b1000"), //8
108        BitPat("b010") -> BitPat("b1000"), //8
109        BitPat("b011") -> BitPat("b0100"), //4
110        BitPat("b100") -> BitPat("b0100"), //4
111        BitPat("b101") -> BitPat("b0010"), //2
112        BitPat("b110") -> BitPat("b0010"), //2
113      ),
114      BitPat.N(4)
115    )
116  )
117  val eNum1HEffect = Mux(isWidenCvt || isNarrowCvt, eNum1H << 1, eNum1H)
118  val eNumMax1H = Mux(lmul.head(1).asBool, eNum1HEffect >> ((~lmul.tail(1)).asUInt +1.U), eNum1HEffect << lmul.tail(1)).asUInt(6, 0)
119  val eNumMax = Mux1H(eNumMax1H, Seq(1,2,4,8,16,32,64).map(i => i.U)) //only for cvt intr, don't exist 128 in cvt
120  val vlForFflags = Mux(vecCtrl.fpu.isFpToVecInst, 1.U, vl)
121  val eNumEffectIdx = Mux(vlForFflags > eNumMax, eNumMax, vlForFflags)
122
123  val eNum = Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num =>num.U))
124  val eStart = vuopIdx * eNum
125  val maskForFflags = Mux(vecCtrl.fpu.isFpToVecInst, allMaskTrue, srcMask)
126  val maskPart = maskForFflags >> eStart
127  val mask =  Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num => maskPart(num-1, 0)))
128  val fflagsEn = Wire(Vec(4 * numVecModule, Bool()))
129
130  fflagsEn := mask.asBools.zipWithIndex.map{case(mask, i) => mask & (eNumEffectIdx > eStart + i.U) }
131
132  val fflagsEnCycle2 = RegEnable(RegEnable(fflagsEn, fire), fireReg)
133  val fflagsAll = Wire(Vec(8, UInt(5.W)))
134  fflagsAll := vfcvtFflags.asTypeOf(fflagsAll)
135  val fflags = fflagsEnCycle2.zip(fflagsAll).map{case(en, fflag) => Mux(en, fflag, 0.U(5.W))}.reduce(_ | _)
136  io.out.bits.res.fflags.get := Mux(outIsMvInst, 0.U, fflags)
137
138
139  /**
140   * [[mgu]]'s in connection
141   */
142  val resultDataUInt = Wire(UInt(dataWidth.W))
143  resultDataUInt := vfcvtResult
144
145  private val narrow = RegEnable(RegEnable(isNarrowCvt, fire), fireReg)
146  private val narrowNeedCat = outVecCtrl.vuopIdx(0).asBool && narrow
147  private val outNarrowVd = Mux(narrowNeedCat, Cat(resultDataUInt(dataWidth / 2 - 1, 0), outOldVd(dataWidth / 2 - 1, 0)),
148                                               Cat(outOldVd(dataWidth - 1, dataWidth / 2), resultDataUInt(dataWidth / 2 - 1, 0)))
149
150  mgu.io.in.vd := resultDataUInt
151  mgu.io.in.vd := Mux(narrow, outNarrowVd, resultDataUInt)
152  mgu.io.in.oldVd := outOldVd
153  mgu.io.in.mask := maskToMgu
154  mgu.io.in.info.ta := outVecCtrl.vta
155  mgu.io.in.info.ma := outVecCtrl.vma
156  mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl)
157  mgu.io.in.info.vlmul := outVecCtrl.vlmul
158  mgu.io.in.info.valid := io.out.valid
159  mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart)
160  mgu.io.in.info.eew := outEew
161  mgu.io.in.info.vsew := outVecCtrl.vsew
162  mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx
163  mgu.io.in.info.narrow := narrow
164  mgu.io.in.info.dstMask := outVecCtrl.isDstMask
165  mgu.io.in.isIndexedVls := false.B
166
167  // for scalar f2i cvt inst
168  val isFp2VecForInt = outVecCtrl.fpu.isFpToVecInst && outIs32bits && outIsInt
169  // for f2i mv inst
170  val result = Mux(outIsMvInst, RegNext(RegNext(vs2.tail(64))), mgu.io.out.vd)
171
172  io.out.bits.res.data := Mux(isFp2VecForInt,
173    Fill(32, result(31)) ## result(31, 0),
174    result
175  )
176  io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal
177}
178
179class VectorCvtTopIO(vlen: Int, xlen: Int) extends Bundle{
180  val fire = Input(Bool())
181  val uopIdx = Input(Bool())
182  val src = Input(Vec(vlen / xlen, UInt(xlen.W)))
183  val opType = Input(UInt(8.W))
184  val sew = Input(UInt(2.W))
185  val rm = Input(UInt(3.W))
186  val outputWidth1H = Input(UInt(4.W))
187  val isWiden = Input(Bool())
188  val isNarrow = Input(Bool())
189  val isFpToVecInst = Input(Bool())
190
191  val result = Output(UInt(vlen.W))
192  val fflags = Output(UInt((vlen/16*5).W))
193}
194
195
196
197//according to uopindex, 1: high64 0:low64
198class VectorCvtTop(vlen: Int, xlen: Int) extends Module{
199  val io = IO(new VectorCvtTopIO(vlen, xlen))
200
201  val (fire, uopIdx, src, opType, sew, rm, outputWidth1H, isWiden, isNarrow, isFpToVecInst) = (
202    io.fire, io.uopIdx, io.src, io.opType, io.sew, io.rm, io.outputWidth1H, io.isWiden, io.isNarrow, io.isFpToVecInst
203  )
204  val fireReg = GatedValidRegNext(fire)
205
206  val in0 = Mux(isWiden && !isFpToVecInst,
207    Mux(uopIdx, src(1).tail(32), src(0).tail(32)),
208    src(0)
209  )
210
211  val in1 = Mux(isWiden,
212    Mux(uopIdx, src(1).head(32), src(0).head(32)),
213    src(1)
214  )
215
216  val vectorCvt0 = Module(new VectorCvt(xlen))
217  vectorCvt0.fire := fire
218  vectorCvt0.src := in0
219  vectorCvt0.opType := opType
220  vectorCvt0.sew := sew
221  vectorCvt0.rm := rm
222  vectorCvt0.isFpToVecInst := isFpToVecInst
223  vectorCvt0.isFround := 0.U
224  vectorCvt0.isFcvtmod := false.B
225
226  val vectorCvt1 = Module(new VectorCvt(xlen))
227  vectorCvt1.fire := fire
228  vectorCvt1.src := in1
229  vectorCvt1.opType := opType
230  vectorCvt1.sew := sew
231  vectorCvt1.rm := rm
232  vectorCvt1.isFpToVecInst := isFpToVecInst
233  vectorCvt1.isFround := 0.U
234  vectorCvt1.isFcvtmod := false.B
235
236  val isNarrowCycle2 = RegEnable(RegEnable(isNarrow, fire), fireReg)
237  val outputWidth1HCycle2 = RegEnable(RegEnable(outputWidth1H, fire), fireReg)
238
239  //cycle2
240  io.result := Mux(isNarrowCycle2,
241    vectorCvt1.io.result.tail(32) ## vectorCvt0.io.result.tail(32),
242    vectorCvt1.io.result ## vectorCvt0.io.result)
243
244  io.fflags := Mux1H(outputWidth1HCycle2, Seq(
245    vectorCvt1.io.fflags ## vectorCvt0.io.fflags,
246    Mux(isNarrowCycle2, vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10), vectorCvt1.io.fflags ## vectorCvt0.io.fflags),
247    Mux(isNarrowCycle2, vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0), vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10)),
248    vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0)
249  ))
250}
251
252
253