1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utility.SignExt 6import xiangshan.backend.decode.ImmUnion 7import xiangshan.backend.fu.{BranchModule, FuConfig, FuncUnit} 8import xiangshan.backend.datapath.DataConfig.VAddrData 9import xiangshan.{RedirectLevel, XSModule} 10 11class AddrAddModule(implicit p: Parameters) extends XSModule { 12 val io = IO(new Bundle { 13 val pc = Input(UInt(VAddrBits.W)) 14 val taken = Input(Bool()) 15 val isRVC = Input(Bool()) 16 val offset = Input(UInt(12.W)) // branch inst only support 12 bits immediate num 17 val target = Output(UInt(XLEN.W)) 18 }) 19 val pcExtend = SignExt(io.pc, VAddrBits + 1) 20 io.target := SignExt(Mux(io.taken, 21 pcExtend + SignExt(ImmUnion.B.toImm32(io.offset), VAddrBits + 1), 22 pcExtend + Mux(io.isRVC, 2.U, 4.U) 23 ), XLEN) 24} 25 26class BranchUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) { 27 val dataModule = Module(new BranchModule) 28 val addModule = Module(new AddrAddModule) 29 dataModule.io.src(0) := io.in.bits.data.src(0) // rs1 30 dataModule.io.src(1) := io.in.bits.data.src(1) // rs2 31 dataModule.io.func := io.in.bits.ctrl.fuOpType 32 dataModule.io.pred_taken := io.in.bits.ctrl.predictInfo.get.taken 33 34 addModule.io.pc := io.in.bits.data.pc.get // pc 35 addModule.io.offset := io.in.bits.data.imm // imm 36 addModule.io.taken := dataModule.io.taken 37 addModule.io.isRVC := io.in.bits.ctrl.preDecode.get.isRVC 38 39 io.out.valid := io.in.valid 40 io.in.ready := io.out.ready 41 42 io.out.bits.res.data := 0.U 43 io.out.bits.res.redirect.get match { 44 case redirect => 45 redirect.valid := io.out.valid && dataModule.io.mispredict 46 redirect.bits := 0.U.asTypeOf(io.out.bits.res.redirect.get.bits) 47 redirect.bits.level := RedirectLevel.flushAfter 48 redirect.bits.robIdx := io.in.bits.ctrl.robIdx 49 redirect.bits.ftqIdx := io.in.bits.ctrl.ftqIdx.get 50 redirect.bits.ftqOffset := io.in.bits.ctrl.ftqOffset.get 51 redirect.bits.fullTarget := addModule.io.target 52 redirect.bits.cfiUpdate.isMisPred := dataModule.io.mispredict 53 redirect.bits.cfiUpdate.taken := dataModule.io.taken 54 redirect.bits.cfiUpdate.predTaken := dataModule.io.pred_taken 55 redirect.bits.cfiUpdate.target := addModule.io.target 56 redirect.bits.cfiUpdate.pc := io.in.bits.data.pc.get 57 redirect.bits.cfiUpdate.backendIAF := io.instrAddrTransType.get.checkAccessFault(addModule.io.target) 58 redirect.bits.cfiUpdate.backendIPF := io.instrAddrTransType.get.checkPageFault(addModule.io.target) 59 redirect.bits.cfiUpdate.backendIGPF := io.instrAddrTransType.get.checkGuestPageFault(addModule.io.target) 60 } 61 connect0LatencyCtrlSingal 62} 63