1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utility.SignExt 6import xiangshan.backend.decode.ImmUnion 7import xiangshan.backend.fu.{BranchModule, FuConfig, FuncUnit} 8import xiangshan.backend.datapath.DataConfig.VAddrData 9import xiangshan.{RedirectLevel, XSModule} 10 11class AddrAddModule(len: Int)(implicit p: Parameters) extends XSModule { 12 val io = IO(new Bundle { 13 val pc = Input(UInt(len.W)) 14 val offset = Input(UInt(12.W)) // branch inst only support 12 bits immediate num 15 val target = Output(UInt(len.W)) 16 }) 17 io.target := io.pc + SignExt(ImmUnion.B.toImm32(io.offset), len) 18} 19 20class BranchUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) { 21 val dataModule = Module(new BranchModule) 22 val addModule = Module(new AddrAddModule(VAddrData().dataWidth)) 23 dataModule.io.src(0) := io.in.bits.data.src(0) // rs1 24 dataModule.io.src(1) := io.in.bits.data.src(1) // rs2 25 dataModule.io.func := io.in.bits.ctrl.fuOpType 26 dataModule.io.pred_taken := io.in.bits.ctrl.predictInfo.get.taken 27 28 addModule.io.pc := io.in.bits.data.pc.get // pc 29 addModule.io.offset := io.in.bits.data.imm // imm 30 31 io.out.valid := io.in.valid 32 io.in.ready := io.out.ready 33 34 io.out.bits.res.data := 0.U 35 io.out.bits.res.redirect.get match { 36 case redirect => 37 redirect.valid := io.out.valid && dataModule.io.mispredict 38 redirect.bits := 0.U.asTypeOf(io.out.bits.res.redirect.get.bits) 39 redirect.bits.level := RedirectLevel.flushAfter 40 redirect.bits.robIdx := io.in.bits.ctrl.robIdx 41 redirect.bits.ftqIdx := io.in.bits.ctrl.ftqIdx.get 42 redirect.bits.ftqOffset := io.in.bits.ctrl.ftqOffset.get 43 redirect.bits.cfiUpdate.isMisPred := dataModule.io.mispredict 44 redirect.bits.cfiUpdate.taken := dataModule.io.taken 45 redirect.bits.cfiUpdate.predTaken := dataModule.io.pred_taken 46 redirect.bits.cfiUpdate.target := addModule.io.target 47 } 48 connect0LatencyCtrlSingal 49} 50