1package xiangshan.backend.fu.vector 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7import xiangshan.backend.fu.FuConfig.VialuCfg 8import xiangshan.backend.fu.vector.Bundles.VConfig 9import xiangshan.backend.fu.vector.utils.ScalaDupToVector 10import xiangshan.backend.fu.{FuConfig, FuncUnit, HasPipelineReg} 11import yunsuan.VialuFixType 12 13trait VecFuncUnitAlias { this: FuncUnit => 14 protected val inCtrl = io.in.bits.ctrl 15 protected val inData = io.in.bits.data 16 protected val vecCtrl = inCtrl.vpu.get 17 18 protected val vill = vecCtrl.vill 19 protected val vma = vecCtrl.vma 20 protected val vta = vecCtrl.vta 21 protected val vsew = vecCtrl.vsew 22 protected val vlmul = vecCtrl.vlmul 23 protected val vm = vecCtrl.vm 24 protected val vstart = vecCtrl.vstart 25 26 protected val frm = io.frm.getOrElse(0.U(3.W)) 27 protected val vxrm = io.vxrm.getOrElse(0.U(3.W)) 28 protected val instRm = inCtrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).rm 29 protected val rm = Mux(vecCtrl.fpu.isFpToVecInst && instRm =/= "b111".U, instRm, frm) 30 protected val vuopIdx = vecCtrl.vuopIdx 31 protected val nf = 0.U // No need to handle nf in vector arith unit 32 33 protected val fuOpType = inCtrl.fuOpType 34 protected val isNarrow = vecCtrl.isNarrow 35 protected val isExt = vecCtrl.isExt 36 protected val isMove = vecCtrl.isMove 37 // swap vs1 and vs2, used by vrsub, etc 38 protected val isReverse = vecCtrl.isReverse 39 40 protected val allMaskTrue = VecInit(Seq.fill(VLEN)(true.B)).asUInt 41 protected val allMaskFalse = VecInit(Seq.fill(VLEN)(false.B)).asUInt 42 43 // vadc.vv, vsbc.vv need this 44 protected val needClearMask: Bool = if(cfg == VialuCfg) VialuFixType.needClearMask(inCtrl.fuOpType) else false.B 45 46 // There is no difference between control-dependency or data-dependency for function unit, 47 // but spliting these in ctrl or data bundles is easy to coding. 48 protected val srcMask: UInt = if(!cfg.maskWakeUp) inCtrl.vpu.get.vmask else { 49 MuxCase(inData.getSrcMask, Seq( 50 needClearMask -> allMaskFalse, 51 vm -> allMaskTrue 52 )) 53 } 54 protected val srcVConfig: VConfig = if(!cfg.vconfigWakeUp) inCtrl.vpu.get.vconfig else inData.getSrcVConfig.asTypeOf(new VConfig) 55 protected val vl = srcVConfig.vl 56} 57 58class VecPipedFuncUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 59 with HasPipelineReg 60 with VecFuncUnitAlias 61{ 62 private val src0 = inData.src(0) 63 private val src1 = WireInit(inData.src(1)) // vs2 only 64 protected val vs2 = src1 65 protected val vs1 = src0 66 protected val oldVd = inData.src(2) 67 68 protected val outCtrl = ctrlVec.last 69 protected val outData = dataVec.last 70 71 protected val outVecCtrl = outCtrl.vpu.get 72 protected val outVm = outVecCtrl.vm 73 74 // vadc.vv, vsbc.vv need this 75 protected val outNeedClearMask: Bool = if(cfg == VialuCfg) VialuFixType.needClearMask(outCtrl.fuOpType) else false.B 76 protected val outVConfig = if(!cfg.vconfigWakeUp) outCtrl.vpu.get.vconfig else outData.getSrcVConfig.asTypeOf(new VConfig) 77 protected val outVl = outVConfig.vl 78 protected val outVstart = outVecCtrl.vstart 79 protected val outOldVd = outData.src(2) 80 protected val outVlmul = outCtrl.vpu.get.vlmul 81 protected val outLastUop = outCtrl.vpu.get.lastUop 82 // There is no difference between control-dependency or data-dependency for function unit, 83 // but spliting these in ctrl or data bundles is easy to coding. 84 protected val outSrcMask: UInt = if (!cfg.maskWakeUp) outCtrl.vpu.get.vmask else { 85 MuxCase( 86 outData.getSrcMask, Seq( 87 outNeedClearMask -> allMaskFalse, 88 outVm -> allMaskTrue 89 ) 90 ) 91 } 92 93 override def latency: Int = cfg.latency.latencyVal.get 94 95} 96