1/**************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 **************************************************************************************** 16 */ 17 18 19package xiangshan.backend.fu.vector 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utils._ 25import utility._ 26import yunsuan.vector.alu.{VAluOpcode, VIAlu, VIntFixpAlu} 27import yunsuan.{VectorElementFormat, VialuFixType} 28import xiangshan.{SelImm, SrcType, UopDivType, XSCoreParamsKey, XSModule} 29import yunsuan.vector.{SewOH, MaskExtract} 30 31 32 33class VIAluFixWrapper(implicit p: Parameters) extends VPUDataModule { 34 35 needReverse := VialuFixType.needReverse(ctrl.fuOpType) 36 needClearMask := VialuFixType.needClearMask(ctrl.fuOpType) 37 38 // connect VIAlu 39 val vIntFixpAlu = Module(new VIntFixpAlu) 40 vIntFixpAlu.io.in.opcode := VialuFixType.getOpcode(in.uop.ctrl.fuOpType) 41 vIntFixpAlu.io.in.info.vm := in.uop.ctrl.vm 42 vIntFixpAlu.io.in.info.ma := in.uop.ctrl.vconfig.vtype.vma 43 vIntFixpAlu.io.in.info.ta := in.uop.ctrl.vconfig.vtype.vta 44 vIntFixpAlu.io.in.info.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 45 vIntFixpAlu.io.in.info.vl := in.uop.ctrl.vconfig.vl 46 47 vIntFixpAlu.io.in.info.vstart := vstart // TODO : 48 vIntFixpAlu.io.in.info.uopIdx := in.uop.ctrl.uopIdx 49 50 vIntFixpAlu.io.in.info.vxrm := vxrm 51 val srcVdType = Wire(new Bundle{ 52 val srcType2 = UInt(4.W) 53 val srcType1 = UInt(4.W) 54 val vdType = UInt(4.W) 55 }) 56 srcVdType := VialuFixType.getSrcVdType(in.uop.ctrl.fuOpType, in.uop.ctrl.vconfig.vtype.vsew(1,0)).asTypeOf(srcVdType.cloneType) 57 vIntFixpAlu.io.in.srcType(0) := srcVdType.srcType2 58 vIntFixpAlu.io.in.srcType(1) := srcVdType.srcType1 59 vIntFixpAlu.io.in.vdType := srcVdType.vdType 60 vIntFixpAlu.io.in.vs1 := vs1 61 vIntFixpAlu.io.in.vs2 := vs2 62 vIntFixpAlu.io.in.old_vd := in.src(2) 63 64 val eewVs1 = SewOH(srcVdType.srcType1(1, 0)) 65 val eewVd = SewOH(srcVdType.vdType(1, 0)) 66 val uopIdx = in.uop.ctrl.uopIdx 67 val narrow = srcVdType.srcType2(1, 0) === 3.U && srcVdType.vdType(1, 0) === 2.U || 68 srcVdType.srcType2(1, 0) === 2.U && srcVdType.vdType(1, 0) === 1.U || 69 srcVdType.srcType2(1, 0) === 1.U && srcVdType.vdType(1, 0) === 0.U 70 val eewVm = Mux(srcVdType.vdType === 15.U, eewVs1, eewVd) 71 val maskIdx = Mux(narrow, uopIdx >> 1, uopIdx) 72 vIntFixpAlu.io.in.mask16b := MaskExtract(mask, maskIdx, eewVm) 73 vIntFixpAlu.io.ctrl.narrow := narrow 74 vIntFixpAlu.io.ctrl.vstart_gte_vl := vstart >= in.uop.ctrl.vconfig.vl 75 76 // connect io 77 io.out.bits.data := vIntFixpAlu.io.out.vd 78 vxsat := vIntFixpAlu.io.out.vxsat 79 io.out.valid := RegNext(io.in.valid) 80} 81 82class VIAluFix(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN) { 83 XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VialuFixType.dummy, "VialuF OpType not supported") 84 override val dataModule = Module(new VIAluFixWrapper) 85 connectDataModule 86} 87