1///**************************************************************************************** 2// * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3// * Copyright (c) 2020-2021 Peng Cheng Laboratory 4// * 5// * XiangShan is licensed under Mulan PSL v2. 6// * You can use this software according to the terms and conditions of the Mulan PSL v2. 7// * You may obtain a copy of Mulan PSL v2 at: 8// * http://license.coscl.org.cn/MulanPSL2 9// * 10// * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11// * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12// * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13// * 14// * See the Mulan PSL v2 for more details. 15// **************************************************************************************** 16// */ 17// 18// 19//package xiangshan.backend.fu.vector 20// 21//import org.chipsalliance.cde.config.Parameters 22//import chisel3._ 23//import utils._ 24//import yunsuan.vector.alu.VIntFixpAlu 25//import yunsuan.VialuFixType 26//import xiangshan.{XSCoreParamsKey, FuType} 27//import yunsuan.vector.{SewOH, MaskExtract} 28// 29// 30// 31//class VIAluFixWrapper(implicit p: Parameters) extends VPUDataModule { 32// 33// needReverse := VialuFixType.needReverse(ctrl.fuOpType) 34// needClearMask := VialuFixType.needClearMask(ctrl.fuOpType) 35// 36// // connect VIAlu 37// val vIntFixpAlu = Module(new VIntFixpAlu) 38// vIntFixpAlu.io.in.opcode := VialuFixType.getOpcode(in.uop.ctrl.fuOpType).asTypeOf(vIntFixpAlu.io.in.opcode) 39// vIntFixpAlu.io.in.info.vm := in.uop.ctrl.vm 40// vIntFixpAlu.io.in.info.ma := in.uop.ctrl.vconfig.vtype.vma 41// vIntFixpAlu.io.in.info.ta := in.uop.ctrl.vconfig.vtype.vta 42// vIntFixpAlu.io.in.info.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 43// vIntFixpAlu.io.in.info.vl := in.uop.ctrl.vconfig.vl 44// 45// vIntFixpAlu.io.in.info.vstart := vstart // TODO : 46// vIntFixpAlu.io.in.info.uopIdx := in.uop.ctrl.uopIdx 47// 48// vIntFixpAlu.io.in.info.vxrm := vxrm 49// val srcVdType = Wire(new Bundle{ 50// val srcType2 = UInt(4.W) 51// val srcType1 = UInt(4.W) 52// val vdType = UInt(4.W) 53// }) 54// srcVdType := VialuFixType.getSrcVdType(in.uop.ctrl.fuOpType, in.uop.ctrl.vconfig.vtype.vsew(1,0)).asTypeOf(srcVdType.cloneType) 55// vIntFixpAlu.io.in.srcType(0) := srcVdType.srcType2 56// vIntFixpAlu.io.in.srcType(1) := srcVdType.srcType1 57// vIntFixpAlu.io.in.vdType := srcVdType.vdType 58// vIntFixpAlu.io.in.vs1 := vs1 59// vIntFixpAlu.io.in.vs2 := vs2 60// vIntFixpAlu.io.in.old_vd := in.src(2) 61// 62// val eewVs1 = SewOH(srcVdType.srcType1(1, 0)) 63// val eewVd = SewOH(srcVdType.vdType(1, 0)) 64// val uopIdx = in.uop.ctrl.uopIdx 65// val narrow = srcVdType.srcType2(1, 0) === 3.U && srcVdType.vdType(1, 0) === 2.U || 66// srcVdType.srcType2(1, 0) === 2.U && srcVdType.vdType(1, 0) === 1.U || 67// srcVdType.srcType2(1, 0) === 1.U && srcVdType.vdType(1, 0) === 0.U 68// val eewVm = Mux(srcVdType.vdType === 15.U, eewVs1, eewVd) 69// val maskIdx = Mux(narrow, uopIdx >> 1, uopIdx) 70// vIntFixpAlu.io.in.mask16b := MaskExtract(mask, maskIdx, eewVm) 71// vIntFixpAlu.io.ctrl.narrow := narrow 72// vIntFixpAlu.io.ctrl.vstart_gte_vl := vstart >= in.uop.ctrl.vconfig.vl 73// 74// // connect io 75// io.out.bits.data := vIntFixpAlu.io.out.vd 76// vxsat := vIntFixpAlu.io.out.vxsat 77// io.out.valid := RegNext(io.in.valid) 78//} 79// 80// 81