xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala (revision 195ef4a53ab54326d879e884c4e1568f424f2668) 
1package xiangshan.backend.fu.vector
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import xiangshan.XSCoreParamsKey
7import xiangshan.backend.decode.isa.bitfield.InstVType
8import xiangshan.backend.fu.VtypeStruct
9import _root_.utils.NamedUInt
10
11object Bundles {
12
13  /**
14    * vtype bundle, should not used as csr reg
15    */
16  class VType(implicit p: Parameters) extends Bundle {
17    val illegal = Bool()
18    val vma     = Bool()
19    val vta     = Bool()
20    val vsew    = VSew()
21    val vlmul   = VLmul()
22  }
23
24  object VType {
25    def apply()(implicit p: Parameters) : VType = {
26      new VType
27    }
28
29    def fromInstVType(instVType: InstVType)(implicit p: Parameters) : VType = {
30      val res = Wire(VType())
31      res.vma   := instVType.vma
32      res.vta   := instVType.vta
33      res.vsew  := instVType.vsew(VSew.width - 1, 0)
34      res.vlmul := instVType.vlmul
35      res.illegal := false.B // Todo: add illegal check function
36      res
37    }
38
39    def fromVtypeStruct(vtypeStruct: VtypeStruct)(implicit p: Parameters): VType = {
40      val res = Wire(VType())
41      res.illegal := vtypeStruct.vill
42      res.vma := vtypeStruct.vma
43      res.vta := vtypeStruct.vta
44      res.vsew := vtypeStruct.vsew(VSew.width - 1, 0)
45      res.vlmul := vtypeStruct.vlmul
46      res
47    }
48
49    def toVtypeStruct(vtype: VType)(implicit p: Parameters) : VtypeStruct = {
50      val res = WireInit(0.U.asTypeOf(new VtypeStruct))
51      res.vill := vtype.illegal
52      res.vma := vtype.vma
53      res.vta := vtype.vta
54      res.vsew := Cat(0.U(1.W), vtype.vsew)
55      res.vlmul := vtype.vlmul
56      res
57    }
58  }
59
60  class VConfig(implicit p: Parameters) extends Bundle {
61    val vtype = new VType
62    val vl    = Vl()
63  }
64
65  object VConfig {
66    def apply()(implicit p: Parameters) : VConfig = {
67      new VConfig()
68    }
69  }
70
71  def mu: UInt = 0.U(1.W)
72  def ma: UInt = 1.U(1.W)
73  def tu: UInt = 0.U(1.W)
74  def ta: UInt = 1.U(1.W)
75
76  // modify the width when support more vector data width
77  object VSew extends NamedUInt(2) {
78    def e8  : UInt = "b000".U(width.W)
79    def e16 : UInt = "b001".U(width.W)
80    def e32 : UInt = "b010".U(width.W)
81    def e64 : UInt = "b011".U(width.W)
82
83    def reserved: BitPat = BitPat("b1??")
84
85    def isReserved(sew: UInt) : Bool = {
86      require(sew.getWidth >= 2 && sew.getWidth <= 3)
87      if (sew.getWidth == 3) {
88        sew === reserved
89      } else {
90        false.B
91      }
92    }
93  }
94
95  object VLmul extends NamedUInt(3) {
96    def m1  : UInt = "b000".U(width.W)
97    def m2  : UInt = "b001".U(width.W)
98    def m4  : UInt = "b010".U(width.W)
99    def m8  : UInt = "b011".U(width.W)
100    def mf2 : UInt = "b111".U(width.W)
101    def mf4 : UInt = "b110".U(width.W)
102    def mf8 : UInt = "b101".U(width.W)
103
104    def reserved: BitPat = BitPat("b100")
105
106    def isReserved(vlmul: UInt) : Bool = {
107      require(vlmul.getWidth == 3)
108      vlmul === reserved
109    }
110  }
111
112  object Vl {
113    def apply()(implicit p: Parameters): UInt = UInt(width.W)
114
115    def width(implicit p: Parameters) = p(XSCoreParamsKey).vlWidth
116  }
117
118  object Vxsat extends NamedUInt(1)
119
120  object Vxrm extends NamedUInt(2)
121
122  object Nf extends NamedUInt(3)
123
124  object VEew extends NamedUInt(3)
125
126  object NumLsElem {
127    def apply()(implicit p: Parameters): UInt = UInt(width.W)
128
129    def width(implicit p: Parameters) = log2Up(p(XSCoreParamsKey).maxElemPerVreg) + 1
130  }
131
132  class Fpu extends Bundle{
133    val isFpToVecInst = Bool()
134    val isFP32Instr   = Bool()
135    val isFP64Instr   = Bool()
136    val isReduction   = Bool()
137    val isFoldTo1_2   = Bool()
138    val isFoldTo1_4   = Bool()
139    val isFoldTo1_8   = Bool()
140  }
141  object Fpu {
142    def apply() = new Fpu
143  }
144}
145