xref: /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala (revision bb2f3f51dd67f6e16e0cc1ffe43368c9fc7e4aef) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17// See LICENSE.Berkeley for license details.
18// See LICENSE.SiFive for license details.
19
20package xiangshan.backend.fu.fpu
21
22import org.chipsalliance.cde.config.Parameters
23import chisel3._
24import chisel3.util._
25import utility.{SignExt, ZeroExt}
26import xiangshan.backend.fu.{FuConfig, FuncUnit, PipedFuncUnit}
27import xiangshan.backend.fu.vector.Bundles.VSew
28import xiangshan.IF2VectorType
29
30class IntFPToVec(cfg: FuConfig)(implicit p: Parameters) extends PipedFuncUnit(cfg) {
31  protected val in = io.in.bits
32  protected val out = io.out.bits
33
34  // vsew is the lowest 2 bits of fuOpType
35  private val isImm = IF2VectorType.isImm(in.ctrl.fuOpType(4, 2))
36  // when needDup is true, the scalar data is duplicated in vector register
37  private val needDup = IF2VectorType.needDup(in.ctrl.fuOpType(4, 2))
38  // when isFmv is true, the high bits of the scalar data is 1
39  private val isFmv = IF2VectorType.isFmv(in.ctrl.fuOpType(4, 2))
40
41  private val isFp = IF2VectorType.isFp(in.ctrl.fuOpType(4, 2))
42
43  // imm use src(1), scalar use src(0)
44  private val scalaData = Mux(isImm, in.data.src(1), in.data.src(0))
45  // vsew is the lowest 2 bits of fuOpType
46  private val vsew = in.ctrl.fuOpType(1, 0)
47  private val dataWidth = cfg.destDataBits
48
49  private val outNAN = Seq(
50    Cat(0.U, Fill(3, 1.U), 1.U, 0.U(3.W)),
51    Cat(0.U, Fill(5, 1.U), 1.U, 0.U(9.W)),
52    Cat(0.U, Fill(8, 1.U), 1.U, 0.U(22.W))
53  )
54  private val isFpCanonicalNAN = Seq(
55    !scalaData.head(56).andR,
56    !scalaData.head(48).andR,
57    !scalaData.head(32).andR
58  )
59
60  private val fpData = Mux1H(Seq(
61    (vsew === VSew.e8)  -> Cat(Fill(56, 1.U), scalaData( 7, 0)),
62    (vsew === VSew.e16) -> Cat(Fill(48, 1.U), scalaData(15, 0)),
63    (vsew === VSew.e32) -> Cat(Fill(32, 1.U), scalaData(31, 0)),
64    (vsew === VSew.e64) -> scalaData
65  ))
66
67  private val vecE8Data  = Wire(Vec(dataWidth /  8, UInt( 8.W)))
68  private val vecE16Data = Wire(Vec(dataWidth / 16, UInt(16.W)))
69  private val vecE32Data = Wire(Vec(dataWidth / 32, UInt(32.W)))
70  private val vecE64Data = Wire(Vec(dataWidth / 64, UInt(64.W)))
71
72  vecE8Data   := VecInit(Seq.fill(dataWidth /  8)(Mux(isFpCanonicalNAN(0) & isFp, outNAN(0), scalaData( 7, 0))))
73  vecE16Data  := VecInit(Seq.fill(dataWidth / 16)(Mux(isFpCanonicalNAN(1) & isFp, outNAN(1), scalaData(15, 0))))
74  vecE32Data  := VecInit(Seq.fill(dataWidth / 32)(Mux(isFpCanonicalNAN(2) & isFp, outNAN(2), scalaData(31, 0))))
75  vecE64Data  := VecInit(Seq.fill(dataWidth / 64)(scalaData(63, 0)))
76  connect0LatencyCtrlSingal
77  out.res.data := Mux(needDup, Mux1H(Seq(
78    (vsew === VSew.e8)  -> vecE8Data.asUInt,
79    (vsew === VSew.e16) -> vecE16Data.asUInt,
80    (vsew === VSew.e32) -> vecE32Data.asUInt,
81    (vsew === VSew.e64) -> vecE64Data.asUInt,
82  )), Mux(isFmv, fpData, scalaData))
83}
84