1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// This file contains components originally written by Yifei He, see 18// https://github.com/OpenXiangShan/XS-Verilog-Library/tree/main/int_div_radix_4_v1 19// Email of original author: [email protected] 20 21package xiangshan.backend.fu 22 23import org.chipsalliance.cde.config.Parameters 24import chisel3._ 25import chisel3.util._ 26import utils._ 27import utility._ 28import xiangshan._ 29import xiangshan.backend.fu.util.CSA3_2 30 31class SRT16DividerDataModule(len: Int) extends Module { 32 val io = IO(new Bundle() { 33 val src = Vec(2, Input(UInt(len.W))) 34 val valid, sign, kill_w, kill_r, isHi, isW = Input(Bool()) 35 val in_ready = Output(Bool()) 36 val out_valid = Output(Bool()) 37 val out_validNext = Output(Bool()) 38 val out_data = Output(UInt(len.W)) 39 val out_ready = Input(Bool()) 40 }) 41 42 // consts 43 val lzc_width = log2Up(len) 44 val itn_len = 1 + len + 2 + 1 45 46 val (a, d, sign, valid, kill_w, kill_r, isHi, isW) = 47 (io.src(0), io.src(1), io.sign, io.valid, io.kill_w, io.kill_r, io.isHi, io.isW) 48 val in_fire = valid && io.in_ready 49 val out_fire = io.out_ready && io.out_valid 50 val newReq = in_fire 51 val s_idle :: s_pre_0 :: s_pre_1 :: s_iter :: s_post_0 :: s_post_1 :: s_finish :: Nil = Enum(7) 52 val quot_neg_2 :: quot_neg_1 :: quot_0 :: quot_pos_1 :: quot_pos_2 :: Nil = Enum(5) 53 54 55 val state = RegInit((1 << s_idle.litValue.toInt).U(7.W)) 56 57 // reused wires 58// val aNormAbs = Wire(UInt((len + 1).W)) // Inputs of xNormAbs regs below 59// val dNormAbs = Wire(UInt((len + 1).W)) 60 val quotIter = Wire(UInt(len.W)) 61 val quotM1Iter = Wire(UInt(len.W)) 62 val aLZC = Wire(UInt((lzc_width + 1).W)) 63 val dLZC = Wire(UInt((lzc_width + 1).W)) 64 65 val rNext = Wire(UInt(itn_len.W)) 66 val rNextPd = Wire(UInt(itn_len.W)) 67 68 val aInverter = Wire(UInt(len.W)) // results of global inverter 69 val dInverter = Wire(UInt(len.W)) 70 71 val finalIter = Wire(Bool()) 72 val special = Wire(Bool()) 73 74 // reused regs 75// val aNormAbsReg = RegEnable(aNormAbs, newReq | state(s_pre_0) | state(s_post_0)) // reg for normalized a & d and rem & rem+d 76// val dNormAbsReg = RegEnable(dNormAbs, newReq | state(s_pre_0) | state(s_post_0)) 77 val quotIterReg = RegEnable(quotIter, state(s_pre_1) | state(s_iter) | state(s_post_0)) 78 val quotM1IterReg = RegEnable(quotM1Iter, state(s_pre_1) | state(s_iter) | state(s_post_0)) 79 val specialReg = RegEnable(special, state(s_pre_1)) 80 val aReg = RegEnable(a, in_fire) 81 82 when(kill_r) { 83 state := UIntToOH(s_idle, 7) 84 } .elsewhen(state(s_idle) && in_fire && !kill_w) { 85 state := UIntToOH(s_pre_0, 7) 86 } .elsewhen(state(s_pre_0)) { // leading zero detection 87 state := UIntToOH(s_pre_1, 7) 88 } .elsewhen(state(s_pre_1)) { // shift a/b 89 state := Mux(special, UIntToOH(s_post_1, 7), UIntToOH(s_iter, 7)) 90 } .elsewhen(state(s_iter)) { // (ws[j+1], wc[j+1]) = 4(ws[j],wc[j]) - q(j+1)*d 91 state := Mux(finalIter, UIntToOH(s_post_0, 7), UIntToOH(s_iter, 7)) 92 } .elsewhen(state(s_post_0)) { // if rem < 0, rem = rem + d 93 state := UIntToOH(s_post_1, 7) 94 } .elsewhen(state(s_post_1)) { 95 state := UIntToOH(s_finish, 7) 96 } .elsewhen(state(s_finish) && io.out_ready) { 97 state := UIntToOH(s_idle, 7) 98 } .otherwise { 99 state := state 100 } 101 102 io.in_ready := state(s_idle) 103 aInverter := -Mux(state(s_idle), a, quotIterReg) // 64, 0 104 dInverter := -Mux(state(s_idle), d, quotM1IterReg) // 64, 0 105 106 val aSign = io.sign && a(len - 1) // 1 107 val dSign = io.sign && d(len - 1) 108 val dSignReg = RegEnable(dSign, newReq) 109 110 val aAbs = Mux(aSign, aInverter, a) // 64, 0 111 val dAbs = Mux(dSign, dInverter, d) 112 val aAbsReg = RegEnable(aAbs, newReq) 113 val dAbsReg = RegEnable(dAbs, newReq) 114 115 val aNorm = (aAbsReg(len - 1, 0) << aLZC(lzc_width - 1, 0))(len - 1, 0) // 64, 65 116 val dNorm = (dAbsReg(len - 1, 0) << dLZC(lzc_width - 1, 0))(len - 1, 0) 117 118 val aNormReg = RegEnable(aNorm, state(s_pre_0)) 119 val dNormReg = RegEnable(dNorm, state(s_pre_0)) 120 121// aNormAbs := Mux1H(Seq( 122// state(s_idle) -> Cat(0.U(1.W), aAbs), // 65, 0 123// state(s_pre_0) -> Cat(0.U(1.W), aNorm), // 65, 0 124// state(s_post_0) -> rNext(len + 3, 3) // remainder 65, 64. highest is sign bit 125// )) 126// dNormAbs := Mux1H(Seq( 127// state(s_idle) -> Cat(0.U(1.W), dAbs), 128// state(s_pre_0) -> Cat(0.U(1.W), dNorm), 129// state(s_post_0) -> rNextPd(len + 3, 3) 130// )) 131 132 // Second cycle, state is pre_0 133 // calculate lzc and move div* and lzc diff check if no_iter_needed 134 135 aLZC := PriorityEncoder(aAbsReg(len - 1, 0).asBools.reverse) 136 dLZC := PriorityEncoder(dAbsReg(len - 1, 0).asBools.reverse) 137 val aLZCReg = RegEnable(aLZC, state(s_pre_0)) // 7, 0 138 val dLZCReg = RegEnable(dLZC, state(s_pre_0)) 139 140 val lzcWireDiff = Cat(0.U(1.W), dLZC(lzc_width - 1, 0)) - Cat(0.U(1.W), aLZC(lzc_width - 1, 0)) // 7, 0 141 val lzcRegDiff = Cat(0.U(1.W), dLZCReg(lzc_width - 1, 0)) - Cat(0.U(1.W), aLZCReg(lzc_width - 1, 0)) 142// val lzcDiff = Mux(state(s_pre_0), lzcWireDiff, lzcRegDiff) 143 144 // special case: 145 // divisor is 1 or -1; dividend has less bits than divisor; divisor is zero 146 // s_pre_0: 147 val dIsOne = dLZC(lzc_width - 1, 0).andR 148 val dIsZero = ~dNormReg.orR 149 val aIsZero = RegEnable(aLZC(lzc_width), state(s_pre_0)) 150 val aTooSmall = RegEnable(aLZC(lzc_width) | lzcWireDiff(lzc_width), state(s_pre_0)) 151 special := dIsOne | dIsZero | aTooSmall 152 153 val quotSpecial = Mux(dIsZero, VecInit(Seq.fill(len)(true.B)).asUInt, 154 Mux(aTooSmall, 0.U, 155 Mux(dSignReg, -aReg, aReg) // signed 2^(len-1) 156 )) 157 val remSpecial = Mux(dIsZero || aTooSmall, aReg, 0.U) 158 val quotSpecialReg = RegEnable(quotSpecial, state(s_pre_1)) 159 val remSpecialReg = RegEnable(remSpecial, state(s_pre_1)) 160 161 // s_pre_1 162 val quotSign = Mux(state(s_idle), aSign ^ dSign, true.B) // if not s_idle then must be s_pre_1 & dIsZero, and that we have 163 val rSign = aSign 164 val quotSignReg = RegEnable(quotSign, in_fire | (state(s_pre_1) & dIsZero)) 165 val rSignReg = RegEnable(rSign, in_fire) 166 167 val rShift = lzcRegDiff(0) 168 val oddIter = lzcRegDiff(1) ^ lzcRegDiff(0) 169 val iterNum = Wire(UInt((lzc_width - 2).W)) 170 val iterNumReg = RegEnable(iterNum, state(s_pre_1) | state(s_iter)) 171 iterNum := Mux(state(s_pre_1), (lzcRegDiff + 1.U) >> 2, iterNumReg -% 1.U) 172 finalIter := iterNumReg === 0.U 173 174 val rSumInit = Cat(0.U(3.W), Mux(rShift, Cat(0.U(1.W), aNormReg), Cat(aNormReg, 0.U(1.W)))) //(1, 67), 0.001xxx 175 val rCarryInit = 0.U(itn_len.W) 176 177 val rSumInitTrunc = Cat(0.U(1.W), rSumInit(itn_len - 4, itn_len - 4 - 4 + 1)) // 0.00___ 178 val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W))( 179 Array( 180 0.U -> "b00100".U(5.W), 181 1.U -> "b00100".U(5.W), 182 2.U -> "b00100".U(5.W), 183 3.U -> "b00110".U(5.W), 184 4.U -> "b00110".U(5.W), 185 5.U -> "b00110".U(5.W), 186 6.U -> "b00110".U(5.W), 187 7.U -> "b01000".U(5.W), 188 ) 189 ) 190 val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W))( 191 Array( 192 0.U -> "b01100".U(5.W), 193 1.U -> "b01110".U(5.W), 194 2.U -> "b01111".U(5.W), 195 3.U -> "b10000".U(5.W), 196 4.U -> "b10010".U(5.W), 197 5.U -> "b10100".U(5.W), 198 6.U -> "b10110".U(5.W), 199 7.U -> "b10110".U(5.W), 200 ) 201 ) 202 val initCmpPos1 = rSumInitTrunc >= mInitPos1 203 val initCmpPos2 = rSumInitTrunc >= mInitPos2 204 val qInit = Mux(initCmpPos2, UIntToOH(quot_pos_2, 5), Mux(initCmpPos1, UIntToOH(quot_pos_1, 5), UIntToOH(quot_0, 5))) 205 206 // in pre_1 we also obtain m_i + 16u * d for all u 207 // udNeg -> (rud, r2ud) -> (rudPmNeg, r2udPmNeg) 208 val dPos = Cat(0.U(1.W), dNormReg) // +d, 0.1xxx, (1, 64) 209 val dNeg = -Cat(0.U(1.W), dNormReg) // -d, 1.xxxx, (1, 64) 210 // val m = Wire(Vec(4, UInt(7.W))) // we have to sigext them to calculate rqd-m_k 211 212 // index 0 is for q=-2 and 4 is for q=2!!! 213 val mNeg = Wire(Vec(4, UInt(12.W))) // selected m, extended to (6, 6) bits 214 val rudNeg = Wire(Vec(5, UInt(10.W))) // (4, 6) 215 val r2udNeg = Wire(Vec(5, UInt(12.W))) // (6, 6) 216 217 // Selection Block with improved timing 218 val rudPmNeg = Wire(Vec(5, Vec(4, UInt(10.W)))) // -(r*u*d+m_k), (5, 5) bits 219 val r2ws = Wire(UInt(10.W)) // r^2*ws (5, 5) bits 220 val r2wc = Wire(UInt(10.W)) 221 // calculating exact values of w 222 val udNeg = Wire(Vec(5, UInt(itn_len.W))) // (3, 65), 1 signExt'ed Bit 223 // val r3udNeg = Wire(Vec(5, UInt(13.W))) 224 225 // Speculative Block 226 val r2udPmNeg = Wire(Vec(5, Vec(4, UInt(13.W)))) // -(r^2*d*d+m_k), (7, 6) bits. 1st index for q 2nd for m 227 val r3ws = Wire(UInt(13.W)) // r^3*ws, (7, 6) bits 228 val r3wc = Wire(UInt(13.W)) 229 val qSpec = Wire(Vec(5, UInt(5.W))) // 5 speculative results of qNext2 230 // output wires 231 val qNext = Wire(UInt(5.W)) 232 val qNext2 = Wire(UInt(5.W)) 233 val rCarryIter = Wire(UInt(itn_len.W)) // (1, 67) 234 val rSumIter = Wire(UInt(itn_len.W)) 235 // val r3wsIter = Wire(UInt(13.W)) 236 // val r3wcIter = Wire(UInt(13.W)) 237 // Input Regs of whole Spec + Sel + sum adder block 238 val qPrevReg = RegEnable(Mux(state(s_pre_1), qInit, qNext2), state(s_pre_1) | state(s_iter)) 239 val rSumReg = RegEnable(Mux(state(s_pre_1), rSumInit, rSumIter), state(s_pre_1) | state(s_iter)) // (1, 67) 240 val rCarryReg = RegEnable(Mux(state(s_pre_1), rCarryInit, rCarryIter), state(s_pre_1) | state(s_iter)) 241 242 // Give values to the regs and wires above... 243 val dForLookup = dPos(len-2, len-4) 244 mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6) 245 Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6) 246 Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)), 247 Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(3)), 11) ,0.U(1.W)) 248 ) 249 udNeg := VecInit( Cat(SignExt(dPos, 66), 0.U(2.W)), 250 Cat(SignExt(dPos, 67), 0.U(1.W)), 251 0.U, 252 Cat(SignExt(dNeg, 67), 0.U(1.W)), 253 Cat(SignExt(dNeg, 66), 0.U(2.W)) 254 ) 255 256 rudNeg := VecInit(Seq.tabulate(5){i => udNeg(i)(itn_len-2, itn_len-11)}) 257 r2udNeg := VecInit(Seq.tabulate(5){i => udNeg(i)(itn_len-2, itn_len-13)}) 258 // r3udNeg := VecInit(Seq.tabulate(5){i => udNeg(i)(itn_len-2, itn_len-13)}) 259 rudPmNeg := VecInit(Seq.tabulate(5){i => VecInit(Seq.tabulate(4){ j => SignExt(rudNeg(i)(9, 1), 10) + mNeg(j)(10, 1)})}) 260 r2udPmNeg := VecInit(Seq.tabulate(5){i => VecInit(Seq.tabulate(4){ j => SignExt(r2udNeg(i), 13) + SignExt(mNeg(j), 13)})}) 261 r3ws := rSumReg(itn_len-1, itn_len-13) 262 r3wc := rCarryReg(itn_len-1, itn_len-13) 263 264 r2ws := rSumReg(itn_len-1, itn_len-10) 265 r2wc := rCarryReg(itn_len-1, itn_len-10) 266 267 val udNegReg = RegEnable(udNeg, state(s_pre_1)) 268// val rudNegReg = RegEnable(rudNeg, state(s_pre_1)) 269 val rudPmNegReg = RegEnable(rudPmNeg, state(s_pre_1)) 270 val r2udPmNegReg = RegEnable(r2udPmNeg, state(s_pre_1)) 271 272 def DetectSign(signs: UInt, name: String): UInt = { 273 val qVec = Wire(Vec(5, Bool())).suggestName(name) 274 qVec(quot_neg_2) := signs(0) && signs(1) && signs(2) 275 qVec(quot_neg_1) := ~signs(0) && signs(1) && signs(2) 276 qVec(quot_0) := signs(2) && ~signs(1) 277 qVec(quot_pos_1) := signs(3) && ~signs(2) && ~signs(1) 278 qVec(quot_pos_2) := ~signs(3) && ~signs(2) && ~signs(1) 279 qVec.asUInt 280 } 281 // Selection block 282 val signs = VecInit(Seq.tabulate(4){ i => { 283 val csa = Module(new CSA3_2(10)).suggestName(s"csa_sel_${i}") 284 csa.io.in(0) := r2ws 285 csa.io.in(1) := r2wc 286 csa.io.in(2) := Mux1H(qPrevReg, rudPmNegReg.toSeq)(i) // rudPmNeg(OHToUInt(qPrevReg))(i) 287 288 (csa.io.out(0) + (csa.io.out(1)(8, 0) << 1))(9) 289 }}) 290 qNext := DetectSign(signs.asUInt, s"sel_q") 291 val csaWide1 = Module(new CSA3_2(itn_len)).suggestName("csa_sel_wide_1") 292 val csaWide2 = Module(new CSA3_2(itn_len)).suggestName("csa_sel_wide_2") 293 csaWide1.io.in(0) := rSumReg << 2 294 csaWide1.io.in(1) := rCarryReg << 2 295 csaWide1.io.in(2) := Mux1H(qPrevReg, udNegReg.toSeq) << 2//udNeg(OHToUInt(qPrevReg)) << 2 296 csaWide2.io.in(0) := csaWide1.io.out(0) << 2 297 csaWide2.io.in(1) := (csaWide1.io.out(1) << 1)(itn_len-1, 0) << 2 298 csaWide2.io.in(2) := Mux1H(qNext, udNegReg.toSeq) << 2 // udNeg(OHToUInt(qNext)) << 2 299 rSumIter := Mux(~oddIter & finalIter, csaWide1.io.out(0), csaWide2.io.out(0)) 300 rCarryIter := Mux(~oddIter & finalIter, (csaWide1.io.out(1) << 1)(itn_len-1, 0), (csaWide2.io.out(1) << 1)(itn_len-1, 0)) 301 // r3wsIter := r3udNeg(OHToUInt(qNext)) 302 // r3wcIter := (csaWide1.io.out(0)(itn_len-3, itn_len-16) + (csaWide1.io.out(1) << 1)(itn_len-3, itn_len-16))(13,1) 303 // Speculative block 304 qSpec := VecInit(Seq.tabulate(5){ q_spec => { 305 val csa1 = Module(new CSA3_2(13)).suggestName(s"csa_spec_${q_spec}") 306 csa1.io.in(0) := r3ws 307 csa1.io.in(1) := r3wc 308 csa1.io.in(2) := SignExt(udNegReg(q_spec)(itn_len-2, itn_len-11), 13) // (4, 6) -> (7, 6) 309 val signs2 = VecInit(Seq.tabulate(4){ i => { 310 val csa2 = Module(new CSA3_2(13)).suggestName(s"csa_spec_${q_spec}_${i}") 311 csa2.io.in(0) := csa1.io.out(0) 312 csa2.io.in(1) := (csa1.io.out(1) << 1)(12, 0) 313 csa2.io.in(2) := Mux1H(qPrevReg, r2udPmNegReg.toSeq)(i) // r2udPmNeg(OHToUInt(qPrevReg))(i) 314 (csa2.io.out(0) + (csa2.io.out(1)(11, 0) << 1))(12) 315 }}) 316 val qVec2 = DetectSign(signs2.asUInt, s"spec_q_${q_spec}") 317 qVec2 318 }}) 319 // qNext2 := qSpec(OHToUInt(qNext)) // TODO: Use Mux1H!! 320 321 qNext2 := Mux1H(qNext, qSpec.toSeq) 322 323 // on the fly quotient conversion 324 val quotHalfIter = Wire(UInt(64.W)) 325 val quotM1HalfIter = Wire(UInt(64.W)) 326 val quotIterNext = Wire(UInt(64.W)) 327 val quotM1IterNext = Wire(UInt(64.W)) 328 def OTFC(q: UInt, quot: UInt, quotM1: UInt): (UInt, UInt) = { 329 val quotNext = Mux1H(Seq( 330 q(quot_pos_2) -> (quot << 2 | "b10".U), 331 q(quot_pos_1) -> (quot << 2 | "b01".U), 332 q(quot_0) -> (quot << 2 | "b00".U), 333 q(quot_neg_1) -> (quotM1 << 2 | "b11".U), 334 q(quot_neg_2) -> (quotM1 << 2 | "b10".U) 335 )) 336 val quotM1Next = Mux1H(Seq( 337 q(quot_pos_2) -> (quot << 2 | "b01".U), 338 q(quot_pos_1) -> (quot << 2 | "b00".U), 339 q(quot_0) -> (quotM1 << 2 | "b11".U), 340 q(quot_neg_1) -> (quotM1 << 2 | "b10".U), 341 q(quot_neg_2) -> (quotM1 << 2 | "b01".U) 342 )) 343 (quotNext(len-1, 0), quotM1Next(len-1, 0)) 344 } 345 quotHalfIter := OTFC(qPrevReg, quotIterReg, quotM1IterReg)._1 346 quotM1HalfIter := OTFC(qPrevReg, quotIterReg, quotM1IterReg)._2 347 quotIterNext := Mux(~oddIter && finalIter, quotHalfIter, OTFC(qNext, quotHalfIter, quotM1HalfIter)._1) 348 quotM1IterNext := Mux(~oddIter && finalIter, quotM1HalfIter, OTFC(qNext, quotHalfIter, quotM1HalfIter)._2) 349 // quotIter := Mux(state(s_pre_1), 0.U(len.W), 350 // Mux(state(s_iter), quotIterNext, 351 // Mux(quotSignReg, aInverter, quotIterReg))) 352 // quotM1Iter := Mux(state(s_pre_1), 353 // 0.U(len.W), Mux(state(s_iter), quotM1IterNext, 354 // Mux(quotSignReg, dInverter, quotM1IterReg))) 355 356 quotIter := Mux(state(s_iter), quotIterNext, 357 Mux(state(s_pre_1), 0.U(len.W), 358 Mux(quotSignReg, aInverter, quotIterReg))) 359 quotM1Iter := Mux(state(s_iter), quotM1IterNext, 360 Mux(state(s_pre_1), 0.U(len.W), 361 Mux(quotSignReg, dInverter, quotM1IterReg))) 362 // finally, to the recovery stages! 363 364 when(rSignReg) { 365 rNext := ~rSumReg + ~rCarryReg + 2.U 366 rNextPd := ~rSumReg + ~rCarryReg + ~Cat(0.U(1.W), dNormReg, 0.U(3.W)) + 3.U 367 } .otherwise { 368 rNext := rSumReg + rCarryReg 369 rNextPd := rSumReg + rCarryReg + Cat(0.U(1.W), dNormReg, 0.U(3.W)) 370 } 371 val rNextReg = RegEnable(rNext(len + 3, 3), state(s_post_0)) 372 val rNextPdReg = RegEnable(rNextPd(len + 3, 3), state(s_post_0)) 373 dontTouch(rNextReg) 374 // post_1 375 val r = rNextReg 376 val rPd = rNextPdReg 377 val rIsZero = ~(r.orR) 378 val needCorr = Mux(rSignReg, ~r(len) & r.orR, r(len)) // when we get pos rem for a<0 or neg rem for a>0 379 val rPreShifted = Mux(needCorr, rPd, r) 380 val rightShifter = Module(new RightShifter(len, lzc_width)) 381 rightShifter.io.in := rPreShifted 382 rightShifter.io.shiftNum := dLZCReg 383 rightShifter.io.msb := Mux(~(rPreShifted.orR), 0.U, rSignReg) 384 val rShifted = rightShifter.io.out 385 val rFinal = RegEnable(Mux(specialReg, remSpecialReg, rShifted), state(s_post_1))// right shifted remainder. shift by the number of bits divisor is shifted 386 val qFinal = RegEnable(Mux(specialReg, quotSpecialReg, Mux(needCorr, quotM1IterReg, quotIterReg)), state(s_post_1)) 387 val res = Mux(isHi, rFinal, qFinal) 388 io.out_data := Mux(isW, 389 SignExt(res(31, 0), len), 390 res 391 ) 392 io.in_ready := state(s_idle) 393 io.out_valid := state(s_finish) 394 io.out_validNext := state(s_post_1) 395} 396 397object mLookUpTable2 { 398 // Usage : 399 // result := decoder(QMCMinimizer, index, mLookupTable.xxx) 400 val minus_m = Seq( 401 Array( // -m[-1] 402 0.U -> "b00_11010".U(7.W), 403 1.U -> "b00_11110".U(7.W), 404 2.U -> "b01_00000".U(7.W), 405 3.U -> "b01_00100".U(7.W), 406 4.U -> "b01_00110".U(7.W), 407 5.U -> "b01_01010".U(7.W), 408 6.U -> "b01_01100".U(7.W), 409 7.U -> "b01_10000".U(7.W) 410 ), 411 Array( // -m[0] 412 0.U -> "b000_0100".U(7.W), 413 1.U -> "b000_0110".U(7.W), 414 2.U -> "b000_0110".U(7.W), 415 3.U -> "b000_0110".U(7.W), 416 4.U -> "b000_1000".U(7.W), 417 5.U -> "b000_1000".U(7.W), 418 6.U -> "b000_1000".U(7.W), 419 7.U -> "b000_1000".U(7.W) 420 ), 421 Array( //-m[1] 422 0.U -> "b111_1101".U(7.W), 423 1.U -> "b111_1100".U(7.W), 424 2.U -> "b111_1100".U(7.W), 425 3.U -> "b111_1100".U(7.W), 426 4.U -> "b111_1011".U(7.W), 427 5.U -> "b111_1010".U(7.W), 428 6.U -> "b111_1010".U(7.W), 429 7.U -> "b111_1010".U(7.W) 430 ), 431 Array( //-m[2] 432 0.U -> "b11_01000".U(7.W), 433 1.U -> "b11_00100".U(7.W), 434 2.U -> "b11_00010".U(7.W), 435 3.U -> "b10_11110".U(7.W), 436 4.U -> "b10_11100".U(7.W), 437 5.U -> "b10_11000".U(7.W), 438 6.U -> "b10_10110".U(7.W), 439 7.U -> "b10_10010".U(7.W) 440 )) 441} 442