| #
c49ebec8 |
| 18-Nov-2024 |
Haoyuan Feng <[email protected]> |
docs: add acknowledgements (#3861)
|
| #
9d9b0bfa |
| 19-Sep-2024 |
junxiong-ji <[email protected]> |
fix(CSR): add a finite state machine in NewCSR (#3597)
CSR instructions used to be executed without pipelining, so a state
machine is not needed inside the CSR module. After adding an
optimization
fix(CSR): add a finite state machine in NewCSR (#3597)
CSR instructions used to be executed without pipelining, so a state
machine is not needed inside the CSR module. After adding an
optimization that allows certain CSRR instructions to be pipelined, a
state machine is required, since the arbiter to integer register files
must allow a write request before a CSRR instructions is successfully
executed.
show more ...
|
| #
e3da8bad |
| 22-Jul-2024 |
Tang Haojin <[email protected]> |
build: purge chisel 3 and add deprecation check (#3250)
|
| #
b9ef0a42 |
| 18-Mar-2024 |
Xuan Hu <[email protected]> |
Merge remote-tracking branch 'upstream/master' into tmp-backend-merge-fixtiming
|
| #
45f43e6e |
| 19-Jan-2024 |
Tang Haojin <[email protected]> |
chore: bump chisel 6.0.0 (#2654)
BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
|
| #
4b0d80d8 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
Merge upstream/master into tmp-backend-merge-master
|
| #
8891a219 |
| 08-Oct-2023 |
Yinan Xu <[email protected]> |
Bump rocket-chip (#2353)
|
| #
935edac4 |
| 21-Sep-2023 |
Tang Haojin <[email protected]> |
chore: remove deprecated brackets, APIs, etc. (#2321)
|
| #
124bf66a |
| 12-Apr-2023 |
Xuan Hu <[email protected]> |
backend,Core: remove dead code and comments
|
| #
07e4f25b |
| 12-Mar-2023 |
Xuan Hu <[email protected]> |
backend: fix div valid signal
The nanhu version make div valid signal ahead of data by one cycle to
optimize timing of wbArbiter. We make `io.valid` signal assert at the
same time of data valid as n
backend: fix div valid signal
The nanhu version make div valid signal ahead of data by one cycle to
optimize timing of wbArbiter. We make `io.valid` signal assert at the
same time of data valid as normal now, and add `io.validNext` signal
which asserts one cycle ahead of `io.valid`.
show more ...
|
| #
67ba96b4 |
| 02-Jan-2023 |
Yinan Xu <[email protected]> |
Switch to asynchronous reset for all modules (#1867)
This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async
Switch to asynchronous reset for all modules (#1867)
This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.
show more ...
|
| #
3c02ee8f |
| 25-Dec-2022 |
wakafa <[email protected]> |
Separate Utility submodule from XiangShan (#1861)
* misc: add utility submodule
* misc: adjust to new utility framework
* bump utility: revert resetgen
* bump huancun
|
| #
1c62c387 |
| 31-Aug-2022 |
Yinan Xu <[email protected]> |
div: enable input buffer to allow more inflights
|
| #
2acd2853 |
| 06-Dec-2021 |
Li Qianruo <[email protected]> |
Fix SRT16div bug with 0 remainder (#1315)
This bug occurs when rem is 0 and dividend is negative
Caused by a buggy rightshifter
|
| #
7eabd47c |
| 01-Dec-2021 |
Li Qianruo <[email protected]> |
Fix div -1 bug (#1285)
|
| #
81cc0e81 |
| 29-Nov-2021 |
Yinan Xu <[email protected]> |
div: enable fast uop out to reduce latency (#1273)
|
| #
f4b2089a |
| 16-Oct-2021 |
Yinan Xu <[email protected]> |
core: use redirect ports for flush (#1121)
This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.
|
| #
f7e0356a |
| 08-Oct-2021 |
Li Qianruo <[email protected]> |
Srt16div Bug Fix (#1089)
* Fix a div 1 bug
* Fix a typo
|
| #
9aca92b9 |
| 28-Sep-2021 |
Yinan Xu <[email protected]> |
misc: code clean up (#1073)
* rename Roq to Rob
* remove trailing whitespaces
* remove unused parameters
|
| #
a58e3351 |
| 23-Sep-2021 |
Li Qianruo <[email protected]> |
Integer SRT16 Divider (#1019)
* New SRT4 divider that may improve timing
See "Digital reurrence dividers with reduced logical depth"
* SRT16 Int Divider that is working properly
* Fix bug r
Integer SRT16 Divider (#1019)
* New SRT4 divider that may improve timing
See "Digital reurrence dividers with reduced logical depth"
* SRT16 Int Divider that is working properly
* Fix bug related to div 1
* Timing improved version of SRT16 int divider
* Add copyright and made some minor changes
* Fix bugs related to div 0
* Fix another div 0 bug
* Fix another special case bug
show more ...
|