1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// This file contains components originally written by Yifei He, see 18// https://github.com/OpenXiangShan/XS-Verilog-Library/tree/main/int_div_radix_4_v1 19// Email of original author: [email protected] 20 21package xiangshan.backend.fu 22 23import chipsalliance.rocketchip.config.Parameters 24import chisel3._ 25import chisel3.util._ 26import utils.SignExt 27import xiangshan.backend.fu.util.CSA3_2 28 29class SRT16DividerDataModule(len: Int) extends Module { 30 val io = IO(new Bundle() { 31 val src = Vec(2, Input(UInt(len.W))) 32 val valid, sign, kill_w, kill_r, isHi, isW = Input(Bool()) 33 val in_ready = Output(Bool()) 34 val out_valid = Output(Bool()) 35 val out_data = Output(UInt(len.W)) 36 val out_ready = Input(Bool()) 37 }) 38 39 // consts 40 val lzc_width = log2Up(len) 41 val itn_len = 1 + len + 2 + 1 42 43 val (a, d, sign, valid, kill_w, kill_r, isHi, isW) = 44 (io.src(0), io.src(1), io.sign, io.valid, io.kill_w, io.kill_r, io.isHi, io.isW) 45 val in_fire = valid && io.in_ready 46 val out_fire = io.out_ready && io.out_valid 47 val newReq = in_fire 48 val s_idle :: s_pre_0 :: s_pre_1 :: s_iter :: s_post_0 :: s_post_1 :: s_finish :: Nil = Enum(7) 49 val quot_neg_2 :: quot_neg_1 :: quot_0 :: quot_pos_1 :: quot_pos_2 :: Nil = Enum(5) 50 51 52 val state = RegInit(UIntToOH(s_idle, 7)) 53 54 // reused wires 55// val aNormAbs = Wire(UInt((len + 1).W)) // Inputs of xNormAbs regs below 56// val dNormAbs = Wire(UInt((len + 1).W)) 57 val quotIter = Wire(UInt(len.W)) 58 val quotM1Iter = Wire(UInt(len.W)) 59 val aLZC = Wire(UInt((lzc_width + 1).W)) 60 val dLZC = Wire(UInt((lzc_width + 1).W)) 61 62 val rNext = Wire(UInt(itn_len.W)) 63 val rNextPd = Wire(UInt(itn_len.W)) 64 65 val aInverter = Wire(UInt(len.W)) // results of global inverter 66 val dInverter = Wire(UInt(len.W)) 67 68 val finalIter = Wire(Bool()) 69 val special = Wire(Bool()) 70 71 // reused regs 72// val aNormAbsReg = RegEnable(aNormAbs, newReq | state(s_pre_0) | state(s_post_0)) // reg for normalized a & d and rem & rem+d 73// val dNormAbsReg = RegEnable(dNormAbs, newReq | state(s_pre_0) | state(s_post_0)) 74 val quotIterReg = RegEnable(quotIter, state(s_pre_1) | state(s_iter) | state(s_post_0)) 75 val quotM1IterReg = RegEnable(quotM1Iter, state(s_pre_1) | state(s_iter) | state(s_post_0)) 76 val specialReg = RegEnable(special, state(s_pre_1)) 77 val aReg = RegEnable(a, in_fire) 78 79 when(kill_r) { 80 state := UIntToOH(s_idle, 7) 81 } .elsewhen(state(s_idle) && in_fire && !kill_w) { 82 state := UIntToOH(s_pre_0, 7) 83 } .elsewhen(state(s_pre_0)) { // leading zero detection 84 state := UIntToOH(s_pre_1, 7) 85 } .elsewhen(state(s_pre_1)) { // shift a/b 86 state := Mux(special, UIntToOH(s_post_1, 7), UIntToOH(s_iter, 7)) 87 } .elsewhen(state(s_iter)) { // (ws[j+1], wc[j+1]) = 4(ws[j],wc[j]) - q(j+1)*d 88 state := Mux(finalIter, UIntToOH(s_post_0, 7), UIntToOH(s_iter, 7)) 89 } .elsewhen(state(s_post_0)) { // if rem < 0, rem = rem + d 90 state := UIntToOH(s_post_1, 7) 91 } .elsewhen(state(s_post_1)) { 92 state := UIntToOH(s_finish, 7) 93 } .elsewhen(state(s_finish) && out_fire) { 94 state := UIntToOH(s_idle, 7) 95 } .otherwise { 96 state := state 97 } 98 99 io.in_ready := state(s_idle) 100 aInverter := -Mux(state(s_idle), a, quotIterReg) // 64, 0 101 dInverter := -Mux(state(s_idle), d, quotM1IterReg) // 64, 0 102 103 val aSign = io.sign && a(len - 1) // 1 104 val dSign = io.sign && d(len - 1) 105 106 val aAbs = Mux(aSign, aInverter, a) // 64, 0 107 val dAbs = Mux(dSign, dInverter, d) 108 val aAbsReg = RegEnable(aAbs, newReq) 109 val dAbsReg = RegEnable(dAbs, newReq) 110 111 val aNorm = (aAbsReg(len - 1, 0) << aLZC(lzc_width - 1, 0))(len - 1, 0) // 64, 65 112 val dNorm = (dAbsReg(len - 1, 0) << dLZC(lzc_width - 1, 0))(len - 1, 0) 113 114 val aNormReg = RegEnable(aNorm, state(s_pre_0)) 115 val dNormReg = RegEnable(dNorm, state(s_pre_0)) 116 117// aNormAbs := Mux1H(Seq( 118// state(s_idle) -> Cat(0.U(1.W), aAbs), // 65, 0 119// state(s_pre_0) -> Cat(0.U(1.W), aNorm), // 65, 0 120// state(s_post_0) -> rNext(len + 3, 3) // remainder 65, 64. highest is sign bit 121// )) 122// dNormAbs := Mux1H(Seq( 123// state(s_idle) -> Cat(0.U(1.W), dAbs), 124// state(s_pre_0) -> Cat(0.U(1.W), dNorm), 125// state(s_post_0) -> rNextPd(len + 3, 3) 126// )) 127 128 // Second cycle, state is pre_0 129 // calculate lzc and move div* and lzc diff check if no_iter_needed 130 131 aLZC := PriorityEncoder(aAbsReg(len - 1, 0).asBools().reverse) 132 dLZC := PriorityEncoder(dAbsReg(len - 1, 0).asBools().reverse) 133 val aLZCReg = RegEnable(aLZC, state(s_pre_0)) // 7, 0 134 val dLZCReg = RegEnable(dLZC, state(s_pre_0)) 135 136 val lzcWireDiff = Cat(0.U(1.W), dLZC(lzc_width - 1, 0)) - Cat(0.U(1.W), aLZC(lzc_width - 1, 0)) // 7, 0 137 val lzcRegDiff = Cat(0.U(1.W), dLZCReg(lzc_width - 1, 0)) - Cat(0.U(1.W), aLZCReg(lzc_width - 1, 0)) 138// val lzcDiff = Mux(state(s_pre_0), lzcWireDiff, lzcRegDiff) 139 140 // special case: 141 // divisor is 1 or -1; dividend has less bits than divisor; divisor is zero 142 // s_pre_0: 143 val dIsOne = dLZC(lzc_width - 1, 0).andR() 144 val dIsZero = ~dNormReg.orR() 145 val aIsZero = RegEnable(aLZC(lzc_width), state(s_pre_0)) 146 val aTooSmall = RegEnable(aLZC(lzc_width) | lzcWireDiff(lzc_width), state(s_pre_0)) 147 special := dIsOne | dIsZero | aTooSmall 148 149 val quotSpecial = Mux(dIsZero, VecInit(Seq.fill(len)(true.B)).asUInt, 150 Mux(aTooSmall, 0.U, 151 Mux(dSign && ~(aReg.andR()), -aReg, aReg) // signed 2^(len-1) 152 )) 153 val remSpecial = Mux(dIsZero, aReg, 154 Mux(aTooSmall, aReg, 0.U)) 155 val quotSpecialReg = RegEnable(quotSpecial, state(s_pre_1)) 156 val remSpecialReg = RegEnable(remSpecial, state(s_pre_1)) 157 158 // s_pre_1 159 val quotSign = Mux(state(s_idle), aSign ^ dSign, true.B) // if not s_idle then must be s_pre_1 & dIsZero, and that we have 160 val rSign = aSign 161 val quotSignReg = RegEnable(quotSign, in_fire | (state(s_pre_1) & dIsZero)) 162 val rSignReg = RegEnable(rSign, in_fire) 163 164 val rShift = lzcRegDiff(0) 165 val oddIter = lzcRegDiff(1) ^ lzcRegDiff(0) 166 val iterNum = Wire(UInt((lzc_width - 2).W)) 167 val iterNumReg = RegEnable(iterNum, state(s_pre_1) | state(s_iter)) 168 iterNum := Mux(state(s_pre_1), (lzcRegDiff + 1.U) >> 2, iterNumReg -% 1.U) 169 finalIter := iterNumReg === 0.U 170 171 val rSumInit = Cat(0.U(3.W), Mux(rShift, Cat(0.U(1.W), aNormReg), Cat(aNormReg, 0.U(1.W)))) //(1, 67), 0.001xxx 172 val rCarryInit = 0.U(itn_len.W) 173 174 val rSumInitTrunc = Cat(0.U(1.W), rSumInit(itn_len - 4, itn_len - 4 - 4 + 1)) // 0.00___ 175 val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W), 176 Array( 177 0.U -> "b00100".U(5.W), 178 1.U -> "b00100".U(5.W), 179 2.U -> "b00100".U(5.W), 180 3.U -> "b00110".U(5.W), 181 4.U -> "b00110".U(5.W), 182 5.U -> "b00110".U(5.W), 183 6.U -> "b00110".U(5.W), 184 7.U -> "b01000".U(5.W), 185 ) 186 ) 187 val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W), 188 Array( 189 0.U -> "b01100".U(5.W), 190 1.U -> "b01110".U(5.W), 191 2.U -> "b01111".U(5.W), 192 3.U -> "b10000".U(5.W), 193 4.U -> "b10010".U(5.W), 194 5.U -> "b10100".U(5.W), 195 6.U -> "b10110".U(5.W), 196 7.U -> "b10110".U(5.W), 197 ) 198 ) 199 val initCmpPos1 = rSumInitTrunc >= mInitPos1 200 val initCmpPos2 = rSumInitTrunc >= mInitPos2 201 val qInit = Mux(initCmpPos2, UIntToOH(quot_pos_2, 5), Mux(initCmpPos1, UIntToOH(quot_pos_1, 5), UIntToOH(quot_0, 5))) 202 203 // in pre_1 we also obtain m_i + 16u * d for all u 204 // udNeg -> (rud, r2ud) -> (rudPmNeg, r2udPmNeg) 205 val dPos = Cat(0.U(1.W), dNormReg) // +d, 0.1xxx, (1, 64) 206 val dNeg = -Cat(0.U(1.W), dNormReg) // -d, 1.xxxx, (1, 64) 207 // val m = Wire(Vec(4, UInt(7.W))) // we have to sigext them to calculate rqd-m_k 208 209 // index 0 is for q=-2 and 4 is for q=2!!! 210 val mNeg = Wire(Vec(4, UInt(12.W))) // selected m, extended to (6, 6) bits 211 val rudNeg = Wire(Vec(5, UInt(10.W))) // (4, 6) 212 val r2udNeg = Wire(Vec(5, UInt(12.W))) // (6, 6) 213 214 // Selection Block with improved timing 215 val rudPmNeg = Wire(Vec(5, Vec(4, UInt(10.W)))) // -(r*u*d+m_k), (5, 5) bits 216 val r2ws = Wire(UInt(10.W)) // r^2*ws (5, 5) bits 217 val r2wc = Wire(UInt(10.W)) 218 // calculating exact values of w 219 val udNeg = Wire(Vec(5, UInt(itn_len.W))) // (3, 65), 1 signExt'ed Bit 220 // val r3udNeg = Wire(Vec(5, UInt(13.W))) 221 222 // Speculative Block 223 val r2udPmNeg = Wire(Vec(5, Vec(4, UInt(13.W)))) // -(r^2*d*d+m_k), (7, 6) bits. 1st index for q 2nd for m 224 val r3ws = Wire(UInt(13.W)) // r^3*ws, (7, 6) bits 225 val r3wc = Wire(UInt(13.W)) 226 val qSpec = Wire(Vec(5, UInt(5.W))) // 5 speculative results of qNext2 227 // output wires 228 val qNext = Wire(UInt(5.W)) 229 val qNext2 = Wire(UInt(5.W)) 230 val rCarryIter = Wire(UInt(itn_len.W)) // (1, 67) 231 val rSumIter = Wire(UInt(itn_len.W)) 232 // val r3wsIter = Wire(UInt(13.W)) 233 // val r3wcIter = Wire(UInt(13.W)) 234 // Input Regs of whole Spec + Sel + sum adder block 235 val qPrevReg = RegEnable(Mux(state(s_pre_1), qInit, qNext2), state(s_pre_1) | state(s_iter)) 236 val rSumReg = RegEnable(Mux(state(s_pre_1), rSumInit, rSumIter), state(s_pre_1) | state(s_iter)) // (1, 67) 237 val rCarryReg = RegEnable(Mux(state(s_pre_1), rCarryInit, rCarryIter), state(s_pre_1) | state(s_iter)) 238 239 // Give values to the regs and wires above... 240 val dForLookup = dPos(len-2, len-4) 241 mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6) 242 Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6) 243 Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)), 244 Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(3)), 11) ,0.U(1.W)) 245 ) 246 udNeg := VecInit( Cat(SignExt(dPos, 66), 0.U(2.W)), 247 Cat(SignExt(dPos, 67), 0.U(1.W)), 248 0.U, 249 Cat(SignExt(dNeg, 67), 0.U(1.W)), 250 Cat(SignExt(dNeg, 66), 0.U(2.W)) 251 ) 252 253 rudNeg := VecInit(Seq.tabulate(5){i => udNeg(i)(itn_len-2, itn_len-11)}) 254 r2udNeg := VecInit(Seq.tabulate(5){i => udNeg(i)(itn_len-2, itn_len-13)}) 255 // r3udNeg := VecInit(Seq.tabulate(5){i => udNeg(i)(itn_len-2, itn_len-13)}) 256 rudPmNeg := VecInit(Seq.tabulate(5){i => VecInit(Seq.tabulate(4){ j => SignExt(rudNeg(i)(9, 1), 10) + mNeg(j)(10, 1)})}) 257 r2udPmNeg := VecInit(Seq.tabulate(5){i => VecInit(Seq.tabulate(4){ j => SignExt(r2udNeg(i), 13) + SignExt(mNeg(j), 13)})}) 258 r3ws := rSumReg(itn_len-1, itn_len-13) 259 r3wc := rCarryReg(itn_len-1, itn_len-13) 260 261 r2ws := rSumReg(itn_len-1, itn_len-10) 262 r2wc := rCarryReg(itn_len-1, itn_len-10) 263 264 val udNegReg = RegEnable(udNeg, state(s_pre_1)) 265// val rudNegReg = RegEnable(rudNeg, state(s_pre_1)) 266 val rudPmNegReg = RegEnable(rudPmNeg, state(s_pre_1)) 267 val r2udPmNegReg = RegEnable(r2udPmNeg, state(s_pre_1)) 268 269 def DetectSign(signs: UInt, name: String): UInt = { 270 val qVec = Wire(Vec(5, Bool())).suggestName(name) 271 qVec(quot_neg_2) := signs(0) && signs(1) && signs(2) 272 qVec(quot_neg_1) := ~signs(0) && signs(1) && signs(2) 273 qVec(quot_0) := signs(2) && ~signs(1) 274 qVec(quot_pos_1) := signs(3) && ~signs(2) && ~signs(1) 275 qVec(quot_pos_2) := ~signs(3) && ~signs(2) && ~signs(1) 276 qVec.asUInt 277 } 278 // Selection block 279 val signs = VecInit(Seq.tabulate(4){ i => { 280 val csa = Module(new CSA3_2(10)).suggestName(s"csa_sel_${i}") 281 csa.io.in(0) := r2ws 282 csa.io.in(1) := r2wc 283 csa.io.in(2) := Mux1H(qPrevReg, rudPmNegReg.toSeq)(i) // rudPmNeg(OHToUInt(qPrevReg))(i) 284 285 (csa.io.out(0) + (csa.io.out(1)(8, 0) << 1))(9) 286 }}) 287 qNext := DetectSign(signs.asUInt, s"sel_q") 288 val csaWide1 = Module(new CSA3_2(itn_len)).suggestName("csa_sel_wide_1") 289 val csaWide2 = Module(new CSA3_2(itn_len)).suggestName("csa_sel_wide_2") 290 csaWide1.io.in(0) := rSumReg << 2 291 csaWide1.io.in(1) := rCarryReg << 2 292 csaWide1.io.in(2) := Mux1H(qPrevReg, udNegReg.toSeq) << 2//udNeg(OHToUInt(qPrevReg)) << 2 293 csaWide2.io.in(0) := csaWide1.io.out(0) << 2 294 csaWide2.io.in(1) := (csaWide1.io.out(1) << 1)(itn_len-1, 0) << 2 295 csaWide2.io.in(2) := Mux1H(qNext, udNegReg.toSeq) << 2 // udNeg(OHToUInt(qNext)) << 2 296 rSumIter := Mux(~oddIter & finalIter, csaWide1.io.out(0), csaWide2.io.out(0)) 297 rCarryIter := Mux(~oddIter & finalIter, (csaWide1.io.out(1) << 1)(itn_len-1, 0), (csaWide2.io.out(1) << 1)(itn_len-1, 0)) 298 // r3wsIter := r3udNeg(OHToUInt(qNext)) 299 // r3wcIter := (csaWide1.io.out(0)(itn_len-3, itn_len-16) + (csaWide1.io.out(1) << 1)(itn_len-3, itn_len-16))(13,1) 300 // Speculative block 301 qSpec := VecInit(Seq.tabulate(5){ q_spec => { 302 val csa1 = Module(new CSA3_2(13)).suggestName(s"csa_spec_${q_spec}") 303 csa1.io.in(0) := r3ws 304 csa1.io.in(1) := r3wc 305 csa1.io.in(2) := SignExt(udNegReg(q_spec)(itn_len-2, itn_len-11), 13) // (4, 6) -> (7, 6) 306 val signs2 = VecInit(Seq.tabulate(4){ i => { 307 val csa2 = Module(new CSA3_2(13)).suggestName(s"csa_spec_${q_spec}_${i}") 308 csa2.io.in(0) := csa1.io.out(0) 309 csa2.io.in(1) := (csa1.io.out(1) << 1)(12, 0) 310 csa2.io.in(2) := Mux1H(qPrevReg, r2udPmNegReg.toSeq)(i) // r2udPmNeg(OHToUInt(qPrevReg))(i) 311 (csa2.io.out(0) + (csa2.io.out(1)(11, 0) << 1))(12) 312 }}) 313 val qVec2 = DetectSign(signs2.asUInt, s"spec_q_${q_spec}") 314 qVec2 315 }}) 316 // qNext2 := qSpec(OHToUInt(qNext)) // TODO: Use Mux1H!! 317 318 qNext2 := Mux1H(qNext, qSpec.toSeq) 319 320 // on the fly quotient conversion 321 val quotHalfIter = Wire(UInt(64.W)) 322 val quotM1HalfIter = Wire(UInt(64.W)) 323 val quotIterNext = Wire(UInt(64.W)) 324 val quotM1IterNext = Wire(UInt(64.W)) 325 def OTFC(q: UInt, quot: UInt, quotM1: UInt): (UInt, UInt) = { 326 val quotNext = Mux1H(Seq( 327 q(quot_pos_2) -> (quot << 2 | "b10".U), 328 q(quot_pos_1) -> (quot << 2 | "b01".U), 329 q(quot_0) -> (quot << 2 | "b00".U), 330 q(quot_neg_1) -> (quotM1 << 2 | "b11".U), 331 q(quot_neg_2) -> (quotM1 << 2 | "b10".U) 332 )) 333 val quotM1Next = Mux1H(Seq( 334 q(quot_pos_2) -> (quot << 2 | "b01".U), 335 q(quot_pos_1) -> (quot << 2 | "b00".U), 336 q(quot_0) -> (quotM1 << 2 | "b11".U), 337 q(quot_neg_1) -> (quotM1 << 2 | "b10".U), 338 q(quot_neg_2) -> (quotM1 << 2 | "b01".U) 339 )) 340 (quotNext(len-1, 0), quotM1Next(len-1, 0)) 341 } 342 quotHalfIter := OTFC(qPrevReg, quotIterReg, quotM1IterReg)._1 343 quotM1HalfIter := OTFC(qPrevReg, quotIterReg, quotM1IterReg)._2 344 quotIterNext := Mux(~oddIter && finalIter, quotHalfIter, OTFC(qNext, quotHalfIter, quotM1HalfIter)._1) 345 quotM1IterNext := Mux(~oddIter && finalIter, quotM1HalfIter, OTFC(qNext, quotHalfIter, quotM1HalfIter)._2) 346 // quotIter := Mux(state(s_pre_1), 0.U(len.W), 347 // Mux(state(s_iter), quotIterNext, 348 // Mux(quotSignReg, aInverter, quotIterReg))) 349 // quotM1Iter := Mux(state(s_pre_1), 350 // 0.U(len.W), Mux(state(s_iter), quotM1IterNext, 351 // Mux(quotSignReg, dInverter, quotM1IterReg))) 352 353 quotIter := Mux(state(s_iter), quotIterNext, 354 Mux(state(s_pre_1), 0.U(len.W), 355 Mux(quotSignReg, aInverter, quotIterReg))) 356 quotM1Iter := Mux(state(s_iter), quotM1IterNext, 357 Mux(state(s_pre_1), 0.U(len.W), 358 Mux(quotSignReg, dInverter, quotM1IterReg))) 359 // finally, to the recovery stages! 360 361 when(rSignReg) { 362 rNext := ~rSumReg + ~rCarryReg + 2.U 363 rNextPd := ~rSumReg + ~rCarryReg + ~Cat(0.U(1.W), dNormReg, 0.U(3.W)) + 3.U 364 } .otherwise { 365 rNext := rSumReg + rCarryReg 366 rNextPd := rSumReg + rCarryReg + Cat(0.U(1.W), dNormReg, 0.U(3.W)) 367 } 368 val rNextReg = RegEnable(rNext(len + 3, 3), state(s_post_0)) 369 val rNextPdReg = RegEnable(rNextPd(len + 3, 3), state(s_post_0)) 370 dontTouch(rNextReg) 371 // post_1 372 val r = rNextReg 373 val rPd = rNextPdReg 374 val rIsZero = ~(r.orR()) 375 val needCorr = Mux(rSignReg, ~r(len) & r.orR(), r(len)) // when we get pos rem for a<0 or neg rem for a>0 376 val rPreShifted = Mux(needCorr, rPd, r) 377 val rightShifter = Module(new RightShifter(len, lzc_width)) 378 rightShifter.io.in := rPreShifted 379 rightShifter.io.shiftNum := dLZCReg 380 rightShifter.io.msb := rSignReg 381 val rShifted = rightShifter.io.out 382 val rFinal = RegEnable(Mux(specialReg, remSpecialReg, rShifted), state(s_post_1))// right shifted remainder. shift by the number of bits divisor is shifted 383 val qFinal = RegEnable(Mux(specialReg, quotSpecialReg, Mux(needCorr, quotM1IterReg, quotIterReg)), state(s_post_1)) 384 385 val res = Mux(isHi, rFinal, qFinal) 386 io.out_data := Mux(isW, 387 SignExt(res(31, 0), len), 388 res 389 ) 390 io.in_ready := state(s_idle) 391 io.out_valid := state(s_finish) 392 393} 394 395object mLookUpTable2 { 396 // Usage : 397 // result := decoder(QMCMinimizer, index, mLookupTable.xxx) 398 val minus_m = Seq( 399 Array( // -m[-1] 400 0.U -> "b00_11010".U(7.W), 401 1.U -> "b00_11110".U(7.W), 402 2.U -> "b01_00000".U(7.W), 403 3.U -> "b01_00100".U(7.W), 404 4.U -> "b01_00110".U(7.W), 405 5.U -> "b01_01010".U(7.W), 406 6.U -> "b01_01100".U(7.W), 407 7.U -> "b01_10000".U(7.W) 408 ), 409 Array( // -m[0] 410 0.U -> "b000_0100".U(7.W), 411 1.U -> "b000_0110".U(7.W), 412 2.U -> "b000_0110".U(7.W), 413 3.U -> "b000_0110".U(7.W), 414 4.U -> "b000_1000".U(7.W), 415 5.U -> "b000_1000".U(7.W), 416 6.U -> "b000_1000".U(7.W), 417 7.U -> "b000_1000".U(7.W) 418 ), 419 Array( //-m[1] 420 0.U -> "b111_1101".U(7.W), 421 1.U -> "b111_1100".U(7.W), 422 2.U -> "b111_1100".U(7.W), 423 3.U -> "b111_1100".U(7.W), 424 4.U -> "b111_1011".U(7.W), 425 5.U -> "b111_1010".U(7.W), 426 6.U -> "b111_1010".U(7.W), 427 7.U -> "b111_1010".U(7.W) 428 ), 429 Array( //-m[2] 430 0.U -> "b11_01000".U(7.W), 431 1.U -> "b11_00100".U(7.W), 432 2.U -> "b11_00010".U(7.W), 433 3.U -> "b10_11110".U(7.W), 434 4.U -> "b10_11100".U(7.W), 435 5.U -> "b10_11000".U(7.W), 436 6.U -> "b10_10110".U(7.W), 437 7.U -> "b10_10010".U(7.W) 438 )) 439} 440 441class SRT16Divider(len: Int)(implicit p: Parameters) extends AbstractDivider(len) { 442 443 val newReq = io.in.fire() 444 445 val uop = io.in.bits.uop 446 val uopReg = RegEnable(uop, newReq) 447 val ctrlReg = RegEnable(ctrl, newReq) 448 449 val divDataModule = Module(new SRT16DividerDataModule(len)) 450 451 val kill_w = uop.roqIdx.needFlush(io.redirectIn, io.flushIn) 452 val kill_r = !divDataModule.io.in_ready && uopReg.roqIdx.needFlush(io.redirectIn, io.flushIn) 453 454 divDataModule.io.src(0) := io.in.bits.src(0) 455 divDataModule.io.src(1) := io.in.bits.src(1) 456 divDataModule.io.valid := io.in.valid 457 divDataModule.io.sign := sign 458 divDataModule.io.kill_w := kill_w 459 divDataModule.io.kill_r := kill_r 460 divDataModule.io.isHi := ctrlReg.isHi 461 divDataModule.io.isW := ctrlReg.isW 462 divDataModule.io.out_ready := io.out.ready 463 464 io.in.ready := divDataModule.io.in_ready 465 io.out.valid := divDataModule.io.out_valid 466 io.out.bits.data := divDataModule.io.out_data 467 io.out.bits.uop := uopReg 468} 469