xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala (revision 25dc4a827ee27e3ccbaf02e8e5134872cba28fcd) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import xiangshan.backend.fu.NewCSR.CSRDefines._
5import xiangshan.backend.fu.NewCSR.CSRDefines.{
6  CSRWARLField => WARL,
7  CSRROField => RO,
8}
9import xiangshan.backend.fu.NewCSR.CSRFunc._
10import xiangshan.backend.fu.vector.Bundles._
11
12import scala.collection.immutable.SeqMap
13
14trait Unprivileged { self: NewCSR with MachineLevel with SupervisorLevel =>
15
16  val fcsr = Module(new CSRModule("Fcsr", new CSRBundle {
17    val NX = WARL(0, wNoFilter)
18    val UF = WARL(1, wNoFilter)
19    val OF = WARL(2, wNoFilter)
20    val DZ = WARL(3, wNoFilter)
21    val NV = WARL(4, wNoFilter)
22    val FRM = WARL(7, 5, wNoFilter)
23  }) {
24    val wAliasFflags = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
25      val NX = WARL(0, wNoFilter)
26      val UF = WARL(1, wNoFilter)
27      val OF = WARL(2, wNoFilter)
28      val DZ = WARL(3, wNoFilter)
29      val NV = WARL(4, wNoFilter)
30    })))
31    val wAliasFfm = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
32      val FRM = WARL(2, 0, wNoFilter)
33    })))
34    val fflags = IO(Output(UInt(64.W)))
35    val frm = IO(Output(UInt(64.W)))
36
37    // write connection
38    this.wfn(reg)(Seq(wAliasFflags, wAliasFfm))
39
40    // read connection
41    fflags := reg.asUInt(4, 0)
42    frm := reg.FRM.asUInt
43  }).setAddr(0x003)
44
45  // vec
46  val vstart = Module(new CSRModule("vstart"))
47    .setAddr(0x008)
48
49  val vcsr = Module(new CSRModule("Vcsr", new CSRBundle {
50    val VXSAT = WARL(0, wNoFilter)
51    val VXRM  = WARL(2, 1, wNoFilter)
52  }) {
53    val wAliasVxsat = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
54      val VXSAT = WARL(0, wNoFilter)
55    })))
56    val wAlisaVxrm = IO(Input(new CSRAddrWriteBundle(new CSRBundle {
57      val VXRM = WARL(1, 0, wNoFilter)
58    })))
59    val vxsat = IO(Output(Vxsat()))
60    val vxrm  = IO(Output(Vxrm()))
61
62    // write connection
63    this.wfn(reg)(Seq(wAliasVxsat, wAlisaVxrm))
64
65    // read connection
66    vxsat := reg.VXSAT.asUInt
67    vxrm  := reg.VXRM.asUInt
68  }).setAddr(0x00F)
69
70  val vl = Module(new CSRModule("vl"))
71    .setAddr(0xC20)
72
73  val vtype = Module(new CSRModule("vtype", new VtypeBundle))
74    .setAddr(0xC21)
75
76  val vlenb = Module(new CSRModule("vlenb"))
77    .setAddr(0xC22)
78
79  val unprivilegedCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], Data)] = SeqMap(
80    0x001 -> (fcsr.wAliasFflags -> fcsr.fflags),
81    0x002 -> (fcsr.wAliasFfm    -> fcsr.frm),
82    0x003 -> (fcsr.w            -> fcsr.rdata),
83    0x008 -> (vstart.w          -> vstart.rdata),
84    0x009 -> (vcsr.wAliasVxsat  -> vcsr.vxsat),
85    0x00A -> (vcsr.wAlisaVxrm   -> vcsr.vxrm),
86    0x00F -> (vcsr.w            -> vcsr.rdata),
87    0xC20 -> (vl.w              -> vl.rdata),
88    0xC21 -> (vtype.w           -> vtype.rdata),
89    0xC22 -> (vlenb.w           -> vlenb.rdata),
90  )
91
92  val unprivilegedCSRMods: Seq[CSRModule[_]] = Seq(
93    fcsr,
94    vcsr,
95    vstart,
96    vl,
97    vtype,
98    vlenb,
99  )
100
101  val unprivilegedCSROutMap: SeqMap[Int, UInt] = SeqMap(
102    0x001 -> fcsr.fflags.asUInt,
103    0x002 -> fcsr.frm.asUInt,
104    0x003 -> fcsr.rdata.asUInt,
105    0x008 -> vcsr.rdata.asUInt,
106    0x009 -> vcsr.vxsat.asUInt,
107    0x00A -> vcsr.vxrm.asUInt,
108    0x00F -> vcsr.rdata.asUInt,
109    0xC20 -> vl.rdata.asUInt,
110    0xC21 -> vtype.rdata.asUInt,
111    0xC22 -> vlenb.rdata.asUInt,
112  )
113}
114
115class VtypeBundle extends CSRBundle {
116  val VILL  = RO(  63)
117  val VMA   = RO(   7)
118  val VTA   = RO(   6)
119  val VSEW  = RO(5, 3)
120  val VLMUL = RO(2, 0)
121}
122