xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala (revision 419e8ce37cfd74db7daaa469385f90983f5ee93f) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5
6class SstcInterruptGen extends Module {
7  val i = IO(Input(new Bundle {
8    val stime      = ValidIO(UInt(64.W))
9    val vstime     = ValidIO(UInt(64.W))
10    val stimecmp   = new Bundle {
11      val wen = Bool()
12      val rdata = UInt(64.W)
13    }
14    val vstimecmp  = new Bundle {
15      val wen = Bool()
16      val rdata = UInt(64.W)
17    }
18    val htimedeltaWen = Bool()
19    val menvcfg = new Bundle {
20      val wen = Bool()
21      val STCE = Bool()
22    }
23    val henvcfg = new Bundle {
24      val wen = Bool()
25      val STCE = Bool()
26    }
27  }))
28  val o = IO(Output(new Bundle {
29    val STIP = Bool()
30    val VSTIP = Bool()
31  }))
32
33  // Guard TIP by envcfg.STCE to avoid wrong assertion of time interrupt
34  o.STIP  := RegEnable(i.stime.bits >= i.stimecmp.rdata && i.menvcfg.STCE, false.B, i.stime.valid || i.stimecmp.wen || i.menvcfg.wen)
35  o.VSTIP := RegEnable(i.vstime.bits >= i.vstimecmp.rdata && i.henvcfg.STCE, false.B, i.vstime.valid || i.vstimecmp.wen || i.htimedeltaWen || i.menvcfg.wen || i.henvcfg.wen)
36}
37