xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala (revision 211d620b07edb797ba35b635d24fef4e7294bae2) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import chisel3.experimental.BundleLiterals._
6import org.chipsalliance.cde.config.Parameters
7import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL, _}
8import xiangshan.backend.fu.NewCSR.CSRFunc._
9import xiangshan.backend.fu.fpu.Bundles.Fflags
10import xiangshan.backend.fu.vector.Bundles.{Vl, Vstart, Vxsat}
11import xiangshan.frontend.BPUCtrl
12import chisel3.experimental.noPrefix
13
14object CSRBundles {
15  class XtvecBundle extends CSRBundle {
16    val mode = XtvecMode(1, 0, wNoFilter).withReset(0.U)
17    val addr = WARL(63, 2, wNoFilter).withReset(0.U)
18  }
19
20  class CauseBundle extends CSRBundle {
21    val Interrupt = RW(63).withReset(0.U)
22    val ExceptionCode = RW(62, 0).withReset(0.U)
23  }
24
25  class Counteren extends CSRBundle {
26    // Todo: remove reset after adding mcounteren in difftest
27    val CY = RW(0).withReset(0.U)
28    val TM = RW(1).withReset(0.U)
29    val IR = RW(2).withReset(0.U)
30    val HPM = RW(31, 3).withReset(0.U)
31  }
32
33  class OneFieldBundle extends CSRBundle {
34    val ALL = RW(63, 0)
35  }
36
37  class FieldInitBundle extends OneFieldBundle {
38    this.ALL.setRW().withReset(0.U)
39  }
40
41  class XtvalBundle extends FieldInitBundle
42
43  class XtinstBundle extends FieldInitBundle
44
45  abstract class EnvCfg extends CSRBundle {
46    // Set all fields not supported as RO in base class
47    val STCE  =      RO(    63)           .withReset(0.U) // Sstc Enable
48    val PBMTE =      RO(    62)           .withReset(0.U) // Svpbmt Enable
49    val ADUE  =      RO(    61)           .withReset(0.U) // Svadu extension Enable
50    val DTE   =      RO(    59)           .withReset(0.U) // Ssdbltrp extension Enable
51    val PMM   =      RO(33, 32)           .withReset(0.U) // Smnpm extension
52    val CBZE  =      RW(     7)           .withReset(1.U) // Zicboz extension
53    val CBCFE =      RW(     6)           .withReset(1.U) // Zicbom extension
54    val CBIE  = EnvCBIE( 5,  4, wNoEffect).withReset(EnvCBIE.Inval) // Zicbom extension
55    val SSE   =      RO(     3)           .withReset(0.U) // Zicfiss extension Enable in S mode
56    val LPE   =      RO(     2)           .withReset(0.U) // Zicfilp extension
57    val FIOM  =      RO(     0)           .withReset(0.U) // Fence of I/O implies Memory
58  }
59
60  class PrivState extends Bundle { self =>
61    val PRVM = PrivMode(0)
62    val V    = VirtMode(0)
63
64    def isModeM: Bool = isModeMImpl()
65
66    def isModeHS: Bool = isModeHSImpl()
67
68    def isModeHU: Bool = isModeHUImpl()
69
70    def isModeVU: Bool = isModeVUImpl()
71
72    def isModeVS: Bool = isModeVSImpl()
73
74    def isModeHUorVU: Bool = this.PrvmIsU()
75
76    def isModeHSorHU: Bool = (this.PrvmIsU() || this.PrvmIsS()) && !this.isVirtual
77
78    def isVirtual: Bool = this.V.isOneOf(VirtMode.On)
79
80    private[this] object PrvmIsM {
81      val v: Bool = dontTouch(WireInit(self.PRVM === PrivMode.M).suggestName("PrvmIsM"))
82      def apply(): Bool = v
83    }
84
85    private[this] object PrvmIsS {
86      val v: Bool = dontTouch(WireInit(self.PRVM === PrivMode.S).suggestName("PrvmIsS"))
87      def apply(): Bool = v
88    }
89
90    private[this] object PrvmIsU {
91      val v: Bool = dontTouch(WireInit(self.PRVM === PrivMode.U).suggestName("PrvmIsU"))
92      def apply(): Bool = v
93    }
94
95    private[this] object isModeMImpl {
96      val v: Bool = dontTouch(WireInit(PrvmIsM()).suggestName("isModeM"))
97      def apply(): Bool = v
98    }
99
100    private[this] object isModeHSImpl {
101      val v: Bool = dontTouch(WireInit(!self.isVirtual && noPrefix(PrvmIsS())).suggestName("isModeHS"))
102      def apply(): Bool = v
103    }
104
105    private[this] object isModeHUImpl {
106      val v: Bool = dontTouch(WireInit(!self.isVirtual && noPrefix(PrvmIsU())).suggestName("isModeHU"))
107      def apply(): Bool = v
108    }
109
110    private[this] object isModeVSImpl {
111      val v: Bool = dontTouch(WireInit(self.isVirtual && noPrefix(PrvmIsS())).suggestName("isModeVS"))
112      def apply(): Bool = v
113    }
114
115    private[this] object isModeVUImpl {
116      val v: Bool = dontTouch(WireInit(self.isVirtual && noPrefix(PrvmIsU())).suggestName("isModeVU"))
117      def apply(): Bool = v
118    }
119
120    // VU < VS < HS < M
121    // HU < HS < M
122    def < (that: PrivState): Bool = {
123      (this.isVirtual && (that.isModeM || that.isModeHS)) ||
124        (this.V === that.V && this.PRVM < that.PRVM)
125    }
126
127    def > (that: PrivState): Bool = {
128      (that.isVirtual && (this.isModeM || this.isModeHS)) ||
129        (that.V === this.V && that.PRVM < this.PRVM)
130    }
131  }
132
133  object PrivState {
134    def ModeM: PrivState = WireInit((new PrivState).Lit(
135      _.PRVM -> PrivMode.M,
136      _.V    -> VirtMode.Off,
137    ))
138
139    def ModeHS: PrivState = WireInit((new PrivState).Lit(
140      _.PRVM -> PrivMode.S,
141      _.V    -> VirtMode.Off,
142    ))
143
144    def ModeHU: PrivState = WireInit((new PrivState).Lit(
145      _.PRVM -> PrivMode.U,
146      _.V    -> VirtMode.Off,
147    ))
148
149    def ModeVS: PrivState = WireInit((new PrivState).Lit(
150      _.PRVM -> PrivMode.S,
151      _.V    -> VirtMode.On,
152    ))
153
154    def ModeVU: PrivState = WireInit((new PrivState).Lit(
155      _.PRVM -> PrivMode.U,
156      _.V    -> VirtMode.On,
157    ))
158  }
159
160  class RobCommitCSR(implicit p: Parameters) extends Bundle {
161    // need contain 8x8
162    val instNum = ValidIO(UInt(7.W))
163    val fflags  = ValidIO(Fflags())
164    val fsDirty = Bool()
165    val vxsat   = ValidIO(Vxsat())
166    val vsDirty = Bool()
167    val vtype   = ValidIO(new CSRVTypeBundle)
168    val vl      = Vl()
169    val vstart  = ValidIO(Vstart())
170  }
171
172  class CSRCustomState(implicit p: Parameters) extends Bundle {
173    // Prefetcher
174    val l1I_pf_enable = Output(Bool())
175    val l2_pf_enable = Output(Bool())
176    val l1D_pf_enable = Output(Bool())
177    val l1D_pf_train_on_hit = Output(Bool())
178    val l1D_pf_enable_agt = Output(Bool())
179    val l1D_pf_enable_pht = Output(Bool())
180    val l1D_pf_active_threshold = Output(UInt(4.W))
181    val l1D_pf_active_stride = Output(UInt(6.W))
182    val l1D_pf_enable_stride = Output(Bool())
183    val l2_pf_store_only = Output(Bool())
184    // ICache
185    val icache_parity_enable = Output(Bool())
186    // Load violation predictor
187    val lvpred_disable = Output(Bool())
188    val no_spec_load = Output(Bool())
189    val storeset_wait_store = Output(Bool())
190    val storeset_no_fast_wakeup = Output(Bool())
191    val lvpred_timeout = Output(UInt(5.W))
192    // Branch predictor
193    val bp_ctrl = Output(new BPUCtrl)
194    // Memory Block
195    val sbuffer_threshold = Output(UInt(4.W))
196    val ldld_vio_check_enable = Output(Bool())
197    val soft_prefetch_enable = Output(Bool())
198    val cache_error_enable = Output(Bool())
199    val uncache_write_outstanding_enable = Output(Bool())
200    val hd_misalign_st_enable = Output(Bool())
201    val hd_misalign_ld_enable = Output(Bool())
202    // Rename
203    val fusion_enable = Output(Bool())
204    val wfi_enable = Output(Bool())
205  }
206}
207