xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision f314f953f8662b52fb1cb39524d66eecbc7f41c4) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5
6import xiangshan._
7import utils._
8
9import FunctionUnit._
10
11/*
12    XiangShan Function Unit
13    A Exu can have one or more function units
14 */
15
16trait HasFuLatency {
17  val latencyVal: Option[Int]
18}
19
20case class CertainLatency(value: Int) extends HasFuLatency{
21  override val latencyVal: Option[Int] = Some(value)
22}
23
24case class UncertainLatency() extends HasFuLatency {
25  override val latencyVal: Option[Int] = None
26}
27
28case class NexusLatency(value: Int) extends HasFuLatency {
29  override val latencyVal: Option[Int] = Some(value)
30}
31
32
33
34case class FuConfig
35(
36  fuType: UInt,
37  numIntSrc: Int,
38  numFpSrc: Int,
39  writeIntRf: Boolean,
40  writeFpRf: Boolean,
41  hasRedirect: Boolean,
42  latency: HasFuLatency = CertainLatency(0)
43)
44
45class FunctionUnitIO extends XSBundle {
46  val in = Flipped(Decoupled(new Bundle {
47    val src1 = Output(UInt(XLEN.W))
48    val src2 = Output(UInt(XLEN.W))
49    val src3 = Output(UInt(XLEN.W))
50    val func = Output(FuOpType())
51  }))
52  val out = Decoupled(Output(UInt(XLEN.W)))
53}
54
55abstract class FunctionUnit(cfg: FuConfig) extends XSModule
56
57object FunctionUnit {
58
59  val csrCfg =
60    FuConfig(FuType.csr, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
61
62  val jmpCfg =
63    FuConfig(FuType.jmp, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
64
65  val i2fCfg =
66    FuConfig(FuType.i2f, 1, 0, writeIntRf = false, writeFpRf = true, hasRedirect = false)
67
68  val aluCfg =
69    FuConfig(FuType.alu, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
70
71  val mulCfg =
72    FuConfig(FuType.mul, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false,
73      UncertainLatency()// CertainLatency(3)
74    )
75
76  val divCfg =
77    FuConfig(FuType.div, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false,
78      UncertainLatency()
79    )
80
81  val fenceCfg =
82    FuConfig(FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false/*NOTE: need redirect but when commit*/)
83
84  val lduCfg =
85    FuConfig(FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false,
86      UncertainLatency()
87    )
88
89  val stuCfg =
90    FuConfig(FuType.stu, 2, 1, writeIntRf = false, writeFpRf = false, hasRedirect = false,
91      UncertainLatency()
92    )
93
94  val mouCfg =
95    FuConfig(FuType.mou, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false,
96      UncertainLatency()
97  )
98
99  val fmacCfg =
100    FuConfig(FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false,
101      CertainLatency(5)
102    )
103
104  val fmiscCfg =
105    FuConfig(FuType.fmisc, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false,
106      CertainLatency(2)
107    )
108
109  val fDivSqrtCfg =
110    FuConfig(FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false,
111      UncertainLatency()
112    )
113}
114