xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision 3e60a3572d209373dba5a6b1c6198ca94a896539) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5
6import xiangshan._
7import utils._
8
9import FunctionUnit._
10
11/*
12    XiangShan Function Unit
13    A Exu can have one or more function units
14 */
15
16trait HasFuLatency {
17  val latencyVal: Option[Int]
18}
19
20case class CertainLatency(value: Int) extends HasFuLatency{
21  override val latencyVal: Option[Int] = Some(value)
22}
23
24case class UncertainLatency() extends HasFuLatency {
25  override val latencyVal: Option[Int] = None
26}
27
28case class NexusLatency(value: Int) extends HasFuLatency {
29  override val latencyVal: Option[Int] = Some(value)
30}
31
32case class FuConfig
33(
34  fuType: UInt,
35  numIntSrc: Int,
36  numFpSrc: Int,
37  writeIntRf: Boolean,
38  writeFpRf: Boolean,
39  hasRedirect: Boolean,
40  latency: HasFuLatency = CertainLatency(0)
41)
42
43class FunctionUnitIO extends XSBundle {
44  val in = Flipped(Decoupled(new Bundle {
45    val src1 = Output(UInt(XLEN.W))
46    val src2 = Output(UInt(XLEN.W))
47    val src3 = Output(UInt(XLEN.W))
48    val func = Output(FuOpType())
49  }))
50  val out = Decoupled(Output(UInt(XLEN.W)))
51}
52
53abstract class FunctionUnit(cfg: FuConfig) extends XSModule
54
55object FunctionUnit {
56
57  val csrCfg =
58    FuConfig(FuType.csr, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
59
60  val jmpCfg =
61    FuConfig(FuType.jmp, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
62
63  val i2fCfg =
64    FuConfig(FuType.i2f, 1, 0, writeIntRf = false, writeFpRf = true, hasRedirect = false)
65
66  val aluCfg =
67    FuConfig(FuType.alu, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
68
69  val mulCfg =
70    FuConfig(FuType.mul, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false,
71      CertainLatency(3)
72    )
73
74  val divCfg =
75    FuConfig(FuType.div, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false,
76      UncertainLatency()
77    )
78
79  val fenceCfg =
80    FuConfig(FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false/*NOTE: need redirect but when commit*/)
81
82  val lduCfg =
83    FuConfig(FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false,
84      UncertainLatency()
85    )
86
87  val stuCfg =
88    FuConfig(FuType.stu, 2, 1, writeIntRf = false, writeFpRf = false, hasRedirect = false,
89      UncertainLatency()
90    )
91
92  val mouCfg =
93    FuConfig(FuType.mou, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false,
94      UncertainLatency()
95  )
96
97  val fmacCfg =
98    FuConfig(FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false,
99      CertainLatency(5)
100    )
101
102  val fmiscCfg =
103    FuConfig(FuType.fmisc, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false,
104      CertainLatency(2)
105    )
106
107  val fDivSqrtCfg =
108    FuConfig(FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false,
109      UncertainLatency()
110    )
111}
112