1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val readVfRf: Boolean = numVfSrc > 0 46 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 47 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 48 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 49 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 50 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 51 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 52 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 53 val writeVfRf: Boolean = writeFpRf || writeVecRf 54 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 55 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 56 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 57 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 58 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 59 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 60 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 61 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 62 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 63 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 64 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 65 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 66 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 67 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 68 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 69 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 70 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 71 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 72 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 73 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 74 75 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 76 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 77 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 78 79 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 80 81 def copyNum: Int = { 82 val setIQ = mutable.Set[IssueBlockParams]() 83 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 84 backendParam.allIssueParams.map{ issueParams => 85 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 86 setIQ.add(issueParams) 87 } 88 } 89 } 90 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 91 1 + setIQ.size / copyDistance 92 } 93 def rdPregIdxWidth: Int = { 94 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 95 } 96 97 def wbPregIdxWidth: Int = { 98 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 99 } 100 101 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 102 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 103 104 /** 105 * Check if this exu has certain latency 106 */ 107 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 108 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 109 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 110 // only load use it 111 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 112 113 /** 114 * Get mapping from FuType to Latency value. 115 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 116 * 117 * @return Map[ [[BigInt]], Latency] 118 */ 119 def fuLatencyMap: Map[FuType.OHType, Int] = { 120 if (latencyCertain) 121 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 122 else if (hasUncertainLatencyVal) 123 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 124 else 125 Map() 126 } 127 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 128 if (latencyCertain) 129 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 130 else if (hasUncertainLatencyVal) 131 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 132 else 133 Map() 134 } 135 136 /** 137 * Get set of latency of function units. 138 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 139 * 140 * @return Set[Latency] 141 */ 142 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 143 144 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 145 146 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 147 148 def intFuLatencyMap: Map[FuType.OHType, Int] = { 149 if (intLatencyCertain) { 150 if (isVfExeUnit) { 151 // vf exe unit writing back to int regfile should delay 1 cycle 152 // vf exe unit need og2 --> delay 1 cycle 153 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 154 } else { 155 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 156 } 157 } 158 else 159 Map() 160 } 161 162 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 163 164 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 165 if (vfLatencyCertain) 166 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 167 else 168 Map() 169 } 170 171 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 172 173 /** 174 * Check if this exu has fixed latency 175 */ 176 def isFixedLatency: Boolean = { 177 if (latencyCertain) 178 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 179 false 180 } 181 182 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 183 184 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 185 186 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 187 188 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 189 190 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 191 192 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 193 194 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 195 196 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 197 198 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 199 200 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 201 202 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 203 204 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 205 206 def hasLoadExu = hasLoadFu || hasHyldaFu 207 208 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 209 210 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 211 212 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 213 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 214 } 215 216 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 217 218 def getWBSource: SchedulerType = { 219 schdType 220 } 221 222 def hasCrossWb: Boolean = { 223 schdType match { 224 case IntScheduler() => writeFpRf || writeVecRf 225 case VfScheduler() => writeIntRf 226 case _ => false 227 } 228 } 229 230 def canAccept(fuType: UInt): Bool = { 231 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 232 } 233 234 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 235 236 def bindBackendParam(param: BackendParams): Unit = { 237 backendParam = param 238 } 239 240 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 241 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 242 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 243 if (this.isIQWakeUpSource) { 244 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 245 } 246 } 247 248 def updateExuIdx(idx: Int): Unit = { 249 this.exuIdx = idx 250 } 251 252 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 253 254 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 255 256 def getIntWBPort = { 257 wbPortConfigs.collectFirst { 258 case x: IntWB => x 259 } 260 } 261 262 def getVfWBPort = { 263 wbPortConfigs.collectFirst { 264 case x: VfWB => x 265 } 266 } 267 268 /** 269 * Get the [[DataConfig]] that this exu need to read 270 */ 271 def pregRdDataCfgSet: Set[DataConfig] = { 272 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 273 } 274 275 /** 276 * Get the [[DataConfig]] that this exu need to write 277 */ 278 def pregWbDataCfgSet: Set[DataConfig] = { 279 this.wbPortConfigs.map(_.dataCfg).toSet 280 } 281 282 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 283 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 284 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 285 286 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 287 288 exuSrcsCfgSet 289 } 290 291 /** 292 * Get the [[DataConfig]] mapped indices of source data of exu 293 * 294 * @example 295 * {{{ 296 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 297 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 298 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 299 * getRfReadSrcIdx(VConfigData()) = Seq(4) 300 * }}} 301 * @return Map[DataConfig -> Seq[indices]] 302 */ 303 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 304 val dataCfgs = DataConfig.RegSrcDataSet 305 val rfRdDataCfgSet = this.getRfReadDataCfgSet 306 dataCfgs.toSeq.map { cfg => 307 ( 308 cfg, 309 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 310 if (set.contains(cfg)) 311 Option(srcIdx) 312 else 313 None 314 }.filter(_.nonEmpty).map(_.get) 315 ) 316 }.toMap 317 } 318 319 def genExuModule(implicit p: Parameters): ExeUnit = { 320 new ExeUnit(this) 321 } 322 323 def genExuInputBundle(implicit p: Parameters): ExuInput = { 324 new ExuInput(this) 325 } 326 327 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 328 new ExuOutput(this) 329 } 330 331 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 332 new ExuBypassBundle(this) 333 } 334} 335