1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.HasXSParameter 7import xiangshan.backend.Bundles.{ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WakeUpConfig 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[WbConfig], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 28 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 29 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 30 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 31 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 32 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 33 val numSrc: Int = fuConfigs.map(_.numSrc).max 34 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 35 val readIntRf: Boolean = numIntSrc > 0 36 val readFpRf: Boolean = numFpSrc > 0 37 val readVecRf: Boolean = numVecSrc > 0 38 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 39 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 40 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 41 val writeVfRf: Boolean = writeFpRf || writeVecRf 42 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 43 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 44 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 45 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 46 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 47 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 48 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 49 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 50 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 51 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 52 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 53 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 54 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 55 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 56 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 57 val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0 58 59 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 60 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 61 62 /** 63 * Check if this exu has certain latency 64 */ 65 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 66 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 67 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 68 69 /** 70 * Get mapping from FuType to Latency value. 71 * If [[latencyCertain]] is false, get empty [[Map]] 72 * 73 * @return Map[FuType, Latency] 74 */ 75 def fuLatencyMap: Map[Int, Int] = { 76 if (latencyCertain) 77 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 78 else 79 Map() 80 } 81 82 /** 83 * Get set of latency of function units. 84 * If [[latencyCertain]] is false, get empty [[Set]] 85 * 86 * @return Set[Latency] 87 */ 88 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 89 90 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 91 92 def intFuLatencyMap: Map[Int, Int] = { 93 if (intLatencyCertain) 94 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 95 else 96 Map() 97 } 98 99 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 100 101 def vfFuLatencyMap: Map[Int, Int] = { 102 if (vfLatencyCertain) 103 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 104 else 105 Map() 106 } 107 108 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 109 110 /** 111 * Check if this exu has fixed latency 112 */ 113 def isFixedLatency: Boolean = { 114 if (latencyCertain) 115 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 116 false 117 } 118 119 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 120 121 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 122 123 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 124 125 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 126 127 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 128 129 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 130 131 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 132 133 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 134 135 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 136 137 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 138 139 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 140 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 141 } 142 143 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 144 145 def getWBSource: SchedulerType = { 146 schdType 147 } 148 149 def hasCrossWb: Boolean = { 150 schdType match { 151 case IntScheduler() => writeFpRf || writeVecRf 152 case VfScheduler() => writeIntRf 153 case _ => false 154 } 155 } 156 157 def canAccept(fuType: UInt): Bool = { 158 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 159 } 160 161 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 162 163 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 164 this.iqWakeUpSourcePairs = cfgs.filter(_.source == this.name) 165 this.iqWakeUpSinkPairs = cfgs.filter(_.sink == this.name) 166 require(this.isIQWakeUpSource && !this.hasUncertainLatency) 167 } 168 169 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 170 171 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 172 173 def getIntWBPort = { 174 wbPortConfigs.collectFirst { 175 case x: IntWB => x 176 } 177 } 178 179 def getVfWBPort = { 180 wbPortConfigs.collectFirst { 181 case x: VfWB => x 182 } 183 } 184 185 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 186 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 187 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 188 189 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 190 191 exuSrcsCfgSet 192 } 193 194 def genExuModule(implicit p: Parameters): ExeUnit = { 195 new ExeUnit(this) 196 } 197 198 def genExuInputBundle(implicit p: Parameters): ExuInput = { 199 new ExuInput(this) 200 } 201 202 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 203 new ExuOutput(this) 204 } 205} 206