1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.HasXSParameter 7import xiangshan.backend.Bundles.{ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WakeUpConfig 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[WbConfig], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 // used in bypass to select data of exu output 28 var exuIdx: Int = -1 29 30 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 31 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 32 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 33 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 34 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 35 val numSrc: Int = fuConfigs.map(_.numSrc).max 36 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 37 val readIntRf: Boolean = numIntSrc > 0 38 val readFpRf: Boolean = numFpSrc > 0 39 val readVecRf: Boolean = numVecSrc > 0 40 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 41 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 42 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 43 val writeVfRf: Boolean = writeFpRf || writeVecRf 44 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 45 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 46 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 47 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 48 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 49 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 50 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 51 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 52 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 53 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 54 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 55 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 56 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 57 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 58 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 59 val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0 60 61 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 62 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 63 64 /** 65 * Check if this exu has certain latency 66 */ 67 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 68 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 69 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 70 71 /** 72 * Get mapping from FuType to Latency value. 73 * If [[latencyCertain]] is false, get empty [[Map]] 74 * 75 * @return Map[FuType, Latency] 76 */ 77 def fuLatencyMap: Map[Int, Int] = { 78 if (latencyCertain) 79 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 80 else 81 Map() 82 } 83 84 /** 85 * Get set of latency of function units. 86 * If [[latencyCertain]] is false, get empty [[Set]] 87 * 88 * @return Set[Latency] 89 */ 90 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 91 92 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 93 94 def intFuLatencyMap: Map[Int, Int] = { 95 if (intLatencyCertain) 96 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 97 else 98 Map() 99 } 100 101 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 102 103 def vfFuLatencyMap: Map[Int, Int] = { 104 if (vfLatencyCertain) 105 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 106 else 107 Map() 108 } 109 110 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 111 112 /** 113 * Check if this exu has fixed latency 114 */ 115 def isFixedLatency: Boolean = { 116 if (latencyCertain) 117 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 118 false 119 } 120 121 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 122 123 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 124 125 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 126 127 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 128 129 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 130 131 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 132 133 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 134 135 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 136 137 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 138 139 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 140 141 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 142 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 143 } 144 145 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 146 147 def getWBSource: SchedulerType = { 148 schdType 149 } 150 151 def hasCrossWb: Boolean = { 152 schdType match { 153 case IntScheduler() => writeFpRf || writeVecRf 154 case VfScheduler() => writeIntRf 155 case _ => false 156 } 157 } 158 159 def canAccept(fuType: UInt): Bool = { 160 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 161 } 162 163 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 164 165 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 166 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 167 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 168 if (this.isIQWakeUpSource) 169 require(!this.hasUncertainLatency, s"${this.name} is IQ wake up source, but has UncertainLatency") 170 } 171 172 def updateExuIdx(idx: Int): Unit = { 173 this.exuIdx = idx 174 } 175 176 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 177 178 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 179 180 def getIntWBPort = { 181 wbPortConfigs.collectFirst { 182 case x: IntWB => x 183 } 184 } 185 186 def getVfWBPort = { 187 wbPortConfigs.collectFirst { 188 case x: VfWB => x 189 } 190 } 191 192 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 193 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 194 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 195 196 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 197 198 exuSrcsCfgSet 199 } 200 201 def genExuModule(implicit p: Parameters): ExeUnit = { 202 new ExeUnit(this) 203 } 204 205 def genExuInputBundle(implicit p: Parameters): ExuInput = { 206 new ExuInput(this) 207 } 208 209 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 210 new ExuOutput(this) 211 } 212} 213