1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, SchedulerType, VfScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 46 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 47 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 48 val writeVfRf: Boolean = writeFpRf || writeVecRf 49 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 50 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 51 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 52 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 53 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 54 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 55 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 56 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 57 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 58 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 59 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 60 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 61 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 62 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 63 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 64 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 65 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 66 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 67 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 68 69 def copyNum: Int = { 70 val setIQ = mutable.Set[IssueBlockParams]() 71 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 72 backendParam.allIssueParams.map{ issueParams => 73 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 74 setIQ.add(issueParams) 75 } 76 } 77 } 78 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 79 1 + setIQ.size / copyDistance 80 } 81 def rdPregIdxWidth: Int = { 82 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 83 } 84 85 def wbPregIdxWidth: Int = { 86 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 87 } 88 89 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 90 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 91 92 /** 93 * Check if this exu has certain latency 94 */ 95 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 96 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 97 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 98 // only load use it 99 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 100 101 /** 102 * Get mapping from FuType to Latency value. 103 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 104 * 105 * @return Map[ [[BigInt]], Latency] 106 */ 107 def fuLatencyMap: Map[FuType.OHType, Int] = { 108 if (latencyCertain) 109 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 110 else if (hasUncertainLatencyVal) 111 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 112 else 113 Map() 114 } 115 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 116 if (latencyCertain) 117 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 118 else if (hasUncertainLatencyVal) 119 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 120 else 121 Map() 122 } 123 124 /** 125 * Get set of latency of function units. 126 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 127 * 128 * @return Set[Latency] 129 */ 130 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 131 132 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 133 134 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 135 136 def intFuLatencyMap: Map[FuType.OHType, Int] = { 137 if (intLatencyCertain) 138 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 139 else 140 Map() 141 } 142 143 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 144 145 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 146 if (vfLatencyCertain) 147 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 148 else 149 Map() 150 } 151 152 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 153 154 /** 155 * Check if this exu has fixed latency 156 */ 157 def isFixedLatency: Boolean = { 158 if (latencyCertain) 159 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 160 false 161 } 162 163 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 164 165 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 166 167 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 168 169 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 170 171 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 172 173 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 174 175 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 176 177 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 178 179 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 180 181 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 182 183 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 184 185 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 186 187 def hasLoadExu = hasLoadFu || hasHyldaFu 188 189 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 190 191 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 192 193 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 194 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 195 } 196 197 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 198 199 def getWBSource: SchedulerType = { 200 schdType 201 } 202 203 def hasCrossWb: Boolean = { 204 schdType match { 205 case IntScheduler() => writeFpRf || writeVecRf 206 case VfScheduler() => writeIntRf 207 case _ => false 208 } 209 } 210 211 def canAccept(fuType: UInt): Bool = { 212 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 213 } 214 215 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 216 217 def bindBackendParam(param: BackendParams): Unit = { 218 backendParam = param 219 } 220 221 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 222 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 223 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 224 if (this.isIQWakeUpSource) { 225 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 226 } 227 } 228 229 def updateExuIdx(idx: Int): Unit = { 230 this.exuIdx = idx 231 } 232 233 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 234 235 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 236 237 def getIntWBPort = { 238 wbPortConfigs.collectFirst { 239 case x: IntWB => x 240 } 241 } 242 243 def getVfWBPort = { 244 wbPortConfigs.collectFirst { 245 case x: VfWB => x 246 } 247 } 248 249 /** 250 * Get the [[DataConfig]] that this exu need to read 251 */ 252 def pregRdDataCfgSet: Set[DataConfig] = { 253 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 254 } 255 256 /** 257 * Get the [[DataConfig]] that this exu need to write 258 */ 259 def pregWbDataCfgSet: Set[DataConfig] = { 260 this.wbPortConfigs.map(_.dataCfg).toSet 261 } 262 263 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 264 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 265 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 266 267 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 268 269 exuSrcsCfgSet 270 } 271 272 /** 273 * Get the [[DataConfig]] mapped indices of source data of exu 274 * 275 * @example 276 * {{{ 277 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 278 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 279 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 280 * getRfReadSrcIdx(VConfigData()) = Seq(4) 281 * }}} 282 * @return Map[DataConfig -> Seq[indices]] 283 */ 284 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 285 val dataCfgs = DataConfig.RegSrcDataSet 286 val rfRdDataCfgSet = this.getRfReadDataCfgSet 287 dataCfgs.toSeq.map { cfg => 288 ( 289 cfg, 290 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 291 if (set.contains(cfg)) 292 Option(srcIdx) 293 else 294 None 295 }.filter(_.nonEmpty).map(_.get) 296 ) 297 }.toMap 298 } 299 300 def genExuModule(implicit p: Parameters): ExeUnit = { 301 new ExeUnit(this) 302 } 303 304 def genExuInputBundle(implicit p: Parameters): ExuInput = { 305 new ExuInput(this) 306 } 307 308 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 309 new ExuOutput(this) 310 } 311 312 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 313 new ExuBypassBundle(this) 314 } 315} 316