1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, SchedulerType, VfScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 46 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 47 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 48 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 49 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 50 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 51 val writeVfRf: Boolean = writeFpRf || writeVecRf 52 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 53 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 54 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 55 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 56 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 57 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 58 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 59 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 60 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 61 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 62 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 63 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 64 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 65 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 66 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 67 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 68 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 69 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 70 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 71 72 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 73 74 def copyNum: Int = { 75 val setIQ = mutable.Set[IssueBlockParams]() 76 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 77 backendParam.allIssueParams.map{ issueParams => 78 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 79 setIQ.add(issueParams) 80 } 81 } 82 } 83 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 84 1 + setIQ.size / copyDistance 85 } 86 def rdPregIdxWidth: Int = { 87 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 88 } 89 90 def wbPregIdxWidth: Int = { 91 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 92 } 93 94 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 95 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 96 97 /** 98 * Check if this exu has certain latency 99 */ 100 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 101 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 102 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 103 // only load use it 104 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 105 106 /** 107 * Get mapping from FuType to Latency value. 108 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 109 * 110 * @return Map[ [[BigInt]], Latency] 111 */ 112 def fuLatencyMap: Map[FuType.OHType, Int] = { 113 if (latencyCertain) 114 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 115 else if (hasUncertainLatencyVal) 116 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 117 else 118 Map() 119 } 120 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 121 if (latencyCertain) 122 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 123 else if (hasUncertainLatencyVal) 124 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 125 else 126 Map() 127 } 128 129 /** 130 * Get set of latency of function units. 131 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 132 * 133 * @return Set[Latency] 134 */ 135 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 136 137 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 138 139 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 140 141 def intFuLatencyMap: Map[FuType.OHType, Int] = { 142 if (intLatencyCertain) 143 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 144 else 145 Map() 146 } 147 148 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 149 150 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 151 if (vfLatencyCertain) 152 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 153 else 154 Map() 155 } 156 157 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 158 159 /** 160 * Check if this exu has fixed latency 161 */ 162 def isFixedLatency: Boolean = { 163 if (latencyCertain) 164 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 165 false 166 } 167 168 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 169 170 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 171 172 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 173 174 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 175 176 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 177 178 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 179 180 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 181 182 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 183 184 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 185 186 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 187 188 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 189 190 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 191 192 def hasLoadExu = hasLoadFu || hasHyldaFu 193 194 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 195 196 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 197 198 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 199 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 200 } 201 202 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 203 204 def getWBSource: SchedulerType = { 205 schdType 206 } 207 208 def hasCrossWb: Boolean = { 209 schdType match { 210 case IntScheduler() => writeFpRf || writeVecRf 211 case VfScheduler() => writeIntRf 212 case _ => false 213 } 214 } 215 216 def canAccept(fuType: UInt): Bool = { 217 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 218 } 219 220 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 221 222 def bindBackendParam(param: BackendParams): Unit = { 223 backendParam = param 224 } 225 226 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 227 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 228 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 229 if (this.isIQWakeUpSource) { 230 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 231 } 232 } 233 234 def updateExuIdx(idx: Int): Unit = { 235 this.exuIdx = idx 236 } 237 238 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 239 240 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 241 242 def getIntWBPort = { 243 wbPortConfigs.collectFirst { 244 case x: IntWB => x 245 } 246 } 247 248 def getVfWBPort = { 249 wbPortConfigs.collectFirst { 250 case x: VfWB => x 251 } 252 } 253 254 /** 255 * Get the [[DataConfig]] that this exu need to read 256 */ 257 def pregRdDataCfgSet: Set[DataConfig] = { 258 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 259 } 260 261 /** 262 * Get the [[DataConfig]] that this exu need to write 263 */ 264 def pregWbDataCfgSet: Set[DataConfig] = { 265 this.wbPortConfigs.map(_.dataCfg).toSet 266 } 267 268 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 269 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 270 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 271 272 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 273 274 exuSrcsCfgSet 275 } 276 277 /** 278 * Get the [[DataConfig]] mapped indices of source data of exu 279 * 280 * @example 281 * {{{ 282 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 283 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 284 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 285 * getRfReadSrcIdx(VConfigData()) = Seq(4) 286 * }}} 287 * @return Map[DataConfig -> Seq[indices]] 288 */ 289 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 290 val dataCfgs = DataConfig.RegSrcDataSet 291 val rfRdDataCfgSet = this.getRfReadDataCfgSet 292 dataCfgs.toSeq.map { cfg => 293 ( 294 cfg, 295 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 296 if (set.contains(cfg)) 297 Option(srcIdx) 298 else 299 None 300 }.filter(_.nonEmpty).map(_.get) 301 ) 302 }.toMap 303 } 304 305 def genExuModule(implicit p: Parameters): ExeUnit = { 306 new ExeUnit(this) 307 } 308 309 def genExuInputBundle(implicit p: Parameters): ExuInput = { 310 new ExuInput(this) 311 } 312 313 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 314 new ExuOutput(this) 315 } 316 317 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 318 new ExuBypassBundle(this) 319 } 320} 321