1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, SchedulerType, VfScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 46 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 47 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 48 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 49 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 50 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 51 val writeVfRf: Boolean = writeFpRf || writeVecRf 52 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 53 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 54 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 55 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 56 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 57 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 58 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 59 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 60 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 61 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 62 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 63 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 64 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 65 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 66 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 67 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 68 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 69 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 70 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 71 72 def copyNum: Int = { 73 val setIQ = mutable.Set[IssueBlockParams]() 74 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 75 backendParam.allIssueParams.map{ issueParams => 76 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 77 setIQ.add(issueParams) 78 } 79 } 80 } 81 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 82 1 + setIQ.size / copyDistance 83 } 84 def rdPregIdxWidth: Int = { 85 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 86 } 87 88 def wbPregIdxWidth: Int = { 89 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 90 } 91 92 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 93 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 94 95 /** 96 * Check if this exu has certain latency 97 */ 98 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 99 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 100 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 101 // only load use it 102 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 103 104 /** 105 * Get mapping from FuType to Latency value. 106 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 107 * 108 * @return Map[ [[BigInt]], Latency] 109 */ 110 def fuLatencyMap: Map[FuType.OHType, Int] = { 111 if (latencyCertain) 112 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 113 else if (hasUncertainLatencyVal) 114 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 115 else 116 Map() 117 } 118 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 119 if (latencyCertain) 120 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 121 else if (hasUncertainLatencyVal) 122 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 123 else 124 Map() 125 } 126 127 /** 128 * Get set of latency of function units. 129 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 130 * 131 * @return Set[Latency] 132 */ 133 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 134 135 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 136 137 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 138 139 def intFuLatencyMap: Map[FuType.OHType, Int] = { 140 if (intLatencyCertain) 141 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 142 else 143 Map() 144 } 145 146 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 147 148 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 149 if (vfLatencyCertain) 150 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 151 else 152 Map() 153 } 154 155 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 156 157 /** 158 * Check if this exu has fixed latency 159 */ 160 def isFixedLatency: Boolean = { 161 if (latencyCertain) 162 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 163 false 164 } 165 166 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 167 168 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 169 170 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 171 172 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 173 174 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 175 176 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 177 178 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 179 180 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 181 182 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 183 184 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 185 186 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 187 188 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 189 190 def hasLoadExu = hasLoadFu || hasHyldaFu 191 192 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 193 194 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 195 196 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 197 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 198 } 199 200 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 201 202 def getWBSource: SchedulerType = { 203 schdType 204 } 205 206 def hasCrossWb: Boolean = { 207 schdType match { 208 case IntScheduler() => writeFpRf || writeVecRf 209 case VfScheduler() => writeIntRf 210 case _ => false 211 } 212 } 213 214 def canAccept(fuType: UInt): Bool = { 215 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 216 } 217 218 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 219 220 def bindBackendParam(param: BackendParams): Unit = { 221 backendParam = param 222 } 223 224 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 225 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 226 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 227 if (this.isIQWakeUpSource) { 228 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 229 } 230 } 231 232 def updateExuIdx(idx: Int): Unit = { 233 this.exuIdx = idx 234 } 235 236 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 237 238 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 239 240 def getIntWBPort = { 241 wbPortConfigs.collectFirst { 242 case x: IntWB => x 243 } 244 } 245 246 def getVfWBPort = { 247 wbPortConfigs.collectFirst { 248 case x: VfWB => x 249 } 250 } 251 252 /** 253 * Get the [[DataConfig]] that this exu need to read 254 */ 255 def pregRdDataCfgSet: Set[DataConfig] = { 256 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 257 } 258 259 /** 260 * Get the [[DataConfig]] that this exu need to write 261 */ 262 def pregWbDataCfgSet: Set[DataConfig] = { 263 this.wbPortConfigs.map(_.dataCfg).toSet 264 } 265 266 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 267 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 268 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 269 270 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 271 272 exuSrcsCfgSet 273 } 274 275 /** 276 * Get the [[DataConfig]] mapped indices of source data of exu 277 * 278 * @example 279 * {{{ 280 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 281 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 282 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 283 * getRfReadSrcIdx(VConfigData()) = Seq(4) 284 * }}} 285 * @return Map[DataConfig -> Seq[indices]] 286 */ 287 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 288 val dataCfgs = DataConfig.RegSrcDataSet 289 val rfRdDataCfgSet = this.getRfReadDataCfgSet 290 dataCfgs.toSeq.map { cfg => 291 ( 292 cfg, 293 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 294 if (set.contains(cfg)) 295 Option(srcIdx) 296 else 297 None 298 }.filter(_.nonEmpty).map(_.get) 299 ) 300 }.toMap 301 } 302 303 def genExuModule(implicit p: Parameters): ExeUnit = { 304 new ExeUnit(this) 305 } 306 307 def genExuInputBundle(implicit p: Parameters): ExuInput = { 308 new ExuInput(this) 309 } 310 311 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 312 new ExuOutput(this) 313 } 314 315 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 316 new ExuBypassBundle(this) 317 } 318} 319