1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, SchedulerType, VfScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 46 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 47 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 48 val writeVfRf: Boolean = writeFpRf || writeVecRf 49 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 50 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 51 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 52 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 53 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 54 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 55 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 56 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 57 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 58 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 59 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 60 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 61 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 62 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 63 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 64 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 65 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 66 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 67 68 def copyNum: Int = { 69 val setIQ = mutable.Set[IssueBlockParams]() 70 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 71 backendParam.allIssueParams.map{ issueParams => 72 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 73 setIQ.add(issueParams) 74 } 75 } 76 } 77 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 78 1 + setIQ.size / copyDistance 79 } 80 def rdPregIdxWidth: Int = { 81 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 82 } 83 84 def wbPregIdxWidth: Int = { 85 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 86 } 87 88 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 89 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 90 91 /** 92 * Check if this exu has certain latency 93 */ 94 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 95 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 96 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 97 // only load use it 98 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 99 100 /** 101 * Get mapping from FuType to Latency value. 102 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 103 * 104 * @return Map[ [[BigInt]], Latency] 105 */ 106 def fuLatencyMap: Map[FuType.OHType, Int] = { 107 if (latencyCertain) 108 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 109 else if (hasUncertainLatencyVal) 110 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 111 else 112 Map() 113 } 114 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 115 if (latencyCertain) 116 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 117 else if (hasUncertainLatencyVal) 118 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 119 else 120 Map() 121 } 122 123 /** 124 * Get set of latency of function units. 125 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 126 * 127 * @return Set[Latency] 128 */ 129 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 130 131 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 132 133 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 134 135 def intFuLatencyMap: Map[FuType.OHType, Int] = { 136 if (intLatencyCertain) 137 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 138 else 139 Map() 140 } 141 142 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 143 144 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 145 if (vfLatencyCertain) 146 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 147 else 148 Map() 149 } 150 151 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 152 153 /** 154 * Check if this exu has fixed latency 155 */ 156 def isFixedLatency: Boolean = { 157 if (latencyCertain) 158 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 159 false 160 } 161 162 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 163 164 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 165 166 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 167 168 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 169 170 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 171 172 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 173 174 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 175 176 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 177 178 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 179 180 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 181 182 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 183 184 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 185 186 def hasLoadExu = hasLoadFu || hasHyldaFu 187 188 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 189 190 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 191 192 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 193 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 194 } 195 196 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 197 198 def getWBSource: SchedulerType = { 199 schdType 200 } 201 202 def hasCrossWb: Boolean = { 203 schdType match { 204 case IntScheduler() => writeFpRf || writeVecRf 205 case VfScheduler() => writeIntRf 206 case _ => false 207 } 208 } 209 210 def canAccept(fuType: UInt): Bool = { 211 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 212 } 213 214 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 215 216 def bindBackendParam(param: BackendParams): Unit = { 217 backendParam = param 218 } 219 220 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 221 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 222 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 223 if (this.isIQWakeUpSource) { 224 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 225 } 226 } 227 228 def updateExuIdx(idx: Int): Unit = { 229 this.exuIdx = idx 230 } 231 232 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 233 234 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 235 236 def getIntWBPort = { 237 wbPortConfigs.collectFirst { 238 case x: IntWB => x 239 } 240 } 241 242 def getVfWBPort = { 243 wbPortConfigs.collectFirst { 244 case x: VfWB => x 245 } 246 } 247 248 /** 249 * Get the [[DataConfig]] that this exu need to read 250 */ 251 def pregRdDataCfgSet: Set[DataConfig] = { 252 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 253 } 254 255 /** 256 * Get the [[DataConfig]] that this exu need to write 257 */ 258 def pregWbDataCfgSet: Set[DataConfig] = { 259 this.wbPortConfigs.map(_.dataCfg).toSet 260 } 261 262 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 263 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 264 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 265 266 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 267 268 exuSrcsCfgSet 269 } 270 271 /** 272 * Get the [[DataConfig]] mapped indices of source data of exu 273 * 274 * @example 275 * {{{ 276 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 277 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 278 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 279 * getRfReadSrcIdx(VConfigData()) = Seq(4) 280 * }}} 281 * @return Map[DataConfig -> Seq[indices]] 282 */ 283 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 284 val dataCfgs = DataConfig.RegSrcDataSet 285 val rfRdDataCfgSet = this.getRfReadDataCfgSet 286 dataCfgs.toSeq.map { cfg => 287 ( 288 cfg, 289 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 290 if (set.contains(cfg)) 291 Option(srcIdx) 292 else 293 None 294 }.filter(_.nonEmpty).map(_.get) 295 ) 296 }.toMap 297 } 298 299 def genExuModule(implicit p: Parameters): ExeUnit = { 300 new ExeUnit(this) 301 } 302 303 def genExuInputBundle(implicit p: Parameters): ExuInput = { 304 new ExuInput(this) 305 } 306 307 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 308 new ExuOutput(this) 309 } 310 311 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 312 new ExuBypassBundle(this) 313 } 314} 315