1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.HasXSParameter 7import xiangshan.backend.Bundles.{ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig} 11import xiangshan.backend.fu.{FuConfig, FuType} 12import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 13 14case class ExeUnitParams( 15 fuConfigs : Seq[FuConfig], 16 wbPortConfigs : Seq[WbConfig], 17 rfrPortConfigs: Seq[Seq[RdConfig]], 18)( 19 implicit 20 val schdType: SchedulerType, 21) { 22 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 23 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 24 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 25 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 26 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 27 val numSrc: Int = fuConfigs.map(_.numSrc).max 28 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 29 val readIntRf: Boolean = numIntSrc > 0 30 val readFpRf: Boolean = numFpSrc > 0 31 val readVecRf: Boolean = numVecSrc > 0 32 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 33 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 34 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 35 val writeVfRf: Boolean = writeFpRf || writeVecRf 36 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 37 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 38 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 39 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 40 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 41 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 42 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 43 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 44 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 45 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 46 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 47 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 48 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 49 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 50 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 51 val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0 52 53 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 54 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 55 56 val latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_&&_) 57 val intLatencyCertain = if (writeIntFuConfigs.nonEmpty) writeIntFuConfigs.map(x => x.latency.latencyVal.nonEmpty).fold(true)(_ && _) else false 58 val vfLatencyCertain = if (writeVfFuConfigs.nonEmpty) writeVfFuConfigs.map(x => x.latency.latencyVal.nonEmpty).fold(true)(_ && _) else false 59 60 val fuLatencyMap: Option[Seq[(Int, Int)]] = if (latencyCertain) Some(fuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None 61 val latencyValMax: Option[Int] = fuLatencyMap.map(x => x.map(_._2).max) 62 63 val intFuLatencyMap = if (intLatencyCertain) Some(writeIntFuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None 64 val intLatencyValMax = intFuLatencyMap.map(x => x.map(_._2).max) 65 66 val vfFuLatencyMap = if (vfLatencyCertain) Some(writeVfFuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None 67 val vfLatencyValMax = vfFuLatencyMap.map(x => x.map(_._2).max) 68 69 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 70 71 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 72 73 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 74 75 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 76 77 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 78 79 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 80 81 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 82 83 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 84 85 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 86 87 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 88 89 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 90 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 91 } 92 93 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 94 95 def getWBSource: SchedulerType = { 96 schdType 97 } 98 99 def hasCrossWb: Boolean = { 100 schdType match { 101 case IntScheduler() => writeFpRf || writeVecRf 102 case VfScheduler() => writeIntRf 103 case _ => false 104 } 105 } 106 107 def canAccept(fuType: UInt): Bool = { 108 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 109 } 110 111 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 112 113 def getIntWBPort = { 114 wbPortConfigs.collectFirst { 115 case x: IntWB => x 116 } 117 } 118 119 def getVfWBPort = { 120 wbPortConfigs.collectFirst { 121 case x: VfWB => x 122 } 123 } 124 125 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 126 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 127 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 128 129 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 130 131 exuSrcsCfgSet 132 } 133 134 def genExuModule(implicit p: Parameters): ExeUnit = { 135 new ExeUnit(this) 136 } 137 138 def genExuInputBundle(implicit p: Parameters): ExuInput = { 139 new ExuInput(this) 140 } 141 142 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 143 new ExuOutput(this) 144 } 145} 146