1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[PregWB], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 // used in bypass to select data of exu output 28 var exuIdx: Int = -1 29 var backendParam: BackendParams = null 30 31 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 32 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 33 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 34 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 35 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 36 val numSrc: Int = fuConfigs.map(_.numSrc).max 37 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 38 val readIntRf: Boolean = numIntSrc > 0 39 val readFpRf: Boolean = numFpSrc > 0 40 val readVecRf: Boolean = numVecSrc > 0 41 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 42 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 43 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 44 val writeVfRf: Boolean = writeFpRf || writeVecRf 45 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 46 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 47 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 48 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 49 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 50 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 51 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 52 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 53 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 54 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 55 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 56 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 57 val needTarget: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 58 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 59 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 60 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 61 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 62 63 def rdPregIdxWidth: Int = { 64 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 65 } 66 67 def wbPregIdxWidth: Int = { 68 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 69 } 70 71 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 72 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 73 74 /** 75 * Check if this exu has certain latency 76 */ 77 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 78 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 79 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 80 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ && _) 81 82 /** 83 * Get mapping from FuType to Latency value. 84 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 85 * 86 * @return Map[ [[BigInt]], Latency] 87 */ 88 def fuLatencyMap: Map[FuType.OHType, Int] = { 89 if (latencyCertain) 90 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 91 else if (hasUncertainLatencyVal) 92 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 93 else 94 Map() 95 } 96 97 /** 98 * Get set of latency of function units. 99 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 100 * 101 * @return Set[Latency] 102 */ 103 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 104 105 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 106 107 def intFuLatencyMap: Map[FuType.OHType, Int] = { 108 if (intLatencyCertain) 109 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 110 else 111 Map() 112 } 113 114 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 115 116 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 117 if (vfLatencyCertain) 118 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 119 else 120 Map() 121 } 122 123 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 124 125 /** 126 * Check if this exu has fixed latency 127 */ 128 def isFixedLatency: Boolean = { 129 if (latencyCertain) 130 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 131 false 132 } 133 134 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 135 136 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 137 138 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 139 140 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 141 142 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 143 144 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 145 146 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 147 148 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 149 150 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 151 152 def hasHybridAddrFu = hasLoadFu && hasStoreAddrFu 153 154 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 155 156 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 157 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 158 } 159 160 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 161 162 def getWBSource: SchedulerType = { 163 schdType 164 } 165 166 def hasCrossWb: Boolean = { 167 schdType match { 168 case IntScheduler() => writeFpRf || writeVecRf 169 case VfScheduler() => writeIntRf 170 case _ => false 171 } 172 } 173 174 def canAccept(fuType: UInt): Bool = { 175 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 176 } 177 178 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 179 180 def bindBackendParam(param: BackendParams): Unit = { 181 backendParam = param 182 } 183 184 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 185 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 186 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 187 if (this.isIQWakeUpSource) { 188 require(!this.hasUncertainLatency || hasLoadFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 189 } 190 } 191 192 def updateExuIdx(idx: Int): Unit = { 193 this.exuIdx = idx 194 } 195 196 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 197 198 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 199 200 def getIntWBPort = { 201 wbPortConfigs.collectFirst { 202 case x: IntWB => x 203 } 204 } 205 206 def getVfWBPort = { 207 wbPortConfigs.collectFirst { 208 case x: VfWB => x 209 } 210 } 211 212 /** 213 * Get the [[DataConfig]] that this exu need to read 214 */ 215 def pregRdDataCfgSet: Set[DataConfig] = { 216 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 217 } 218 219 /** 220 * Get the [[DataConfig]] that this exu need to write 221 */ 222 def pregWbDataCfgSet: Set[DataConfig] = { 223 this.wbPortConfigs.map(_.dataCfg).toSet 224 } 225 226 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 227 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 228 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 229 230 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 231 232 exuSrcsCfgSet 233 } 234 235 /** 236 * Get the [[DataConfig]] mapped indices of source data of exu 237 * 238 * @example 239 * {{{ 240 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 241 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 242 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 243 * getRfReadSrcIdx(VConfigData()) = Seq(4) 244 * }}} 245 * @return Map[DataConfig -> Seq[indices]] 246 */ 247 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 248 val dataCfgs = DataConfig.RegSrcDataSet 249 val rfRdDataCfgSet = this.getRfReadDataCfgSet 250 dataCfgs.toSeq.map { cfg => 251 ( 252 cfg, 253 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 254 if (set.contains(cfg)) 255 Option(srcIdx) 256 else 257 None 258 }.filter(_.nonEmpty).map(_.get) 259 ) 260 }.toMap 261 } 262 263 def genExuModule(implicit p: Parameters): ExeUnit = { 264 new ExeUnit(this) 265 } 266 267 def genExuInputBundle(implicit p: Parameters): ExuInput = { 268 new ExuInput(this) 269 } 270 271 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 272 new ExuOutput(this) 273 } 274 275 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 276 new ExuBypassBundle(this) 277 } 278} 279