1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[PregWB], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 // used in bypass to select data of exu output 28 var exuIdx: Int = -1 29 var backendParam: BackendParams = null 30 31 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 32 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 33 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 34 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 35 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 36 val numSrc: Int = fuConfigs.map(_.numSrc).max 37 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 38 val readIntRf: Boolean = numIntSrc > 0 39 val readFpRf: Boolean = numFpSrc > 0 40 val readVecRf: Boolean = numVecSrc > 0 41 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 42 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 43 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 44 val writeVfRf: Boolean = writeFpRf || writeVecRf 45 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 46 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 47 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 48 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 49 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 50 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 51 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 52 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 53 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 54 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 55 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 56 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 57 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 58 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 59 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 60 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 61 62 def rdPregIdxWidth: Int = { 63 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 64 } 65 66 def wbPregIdxWidth: Int = { 67 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 68 } 69 70 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 71 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 72 73 /** 74 * Check if this exu has certain latency 75 */ 76 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 77 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 78 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 79 80 /** 81 * Get mapping from FuType to Latency value. 82 * If [[latencyCertain]] is false, get empty [[Map]] 83 * 84 * @return Map[FuType, Latency] 85 */ 86 def fuLatencyMap: Map[Int, Int] = { 87 if (latencyCertain) 88 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 89 else 90 Map() 91 } 92 93 /** 94 * Get set of latency of function units. 95 * If [[latencyCertain]] is false, get empty [[Set]] 96 * 97 * @return Set[Latency] 98 */ 99 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 100 101 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 102 103 def intFuLatencyMap: Map[Int, Int] = { 104 if (intLatencyCertain) 105 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 106 else 107 Map() 108 } 109 110 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 111 112 def vfFuLatencyMap: Map[Int, Int] = { 113 if (vfLatencyCertain) 114 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 115 else 116 Map() 117 } 118 119 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 120 121 /** 122 * Check if this exu has fixed latency 123 */ 124 def isFixedLatency: Boolean = { 125 if (latencyCertain) 126 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 127 false 128 } 129 130 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 131 132 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 133 134 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 135 136 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 137 138 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 139 140 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 141 142 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 143 144 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 145 146 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 147 148 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 149 150 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 151 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 152 } 153 154 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 155 156 def getWBSource: SchedulerType = { 157 schdType 158 } 159 160 def hasCrossWb: Boolean = { 161 schdType match { 162 case IntScheduler() => writeFpRf || writeVecRf 163 case VfScheduler() => writeIntRf 164 case _ => false 165 } 166 } 167 168 def canAccept(fuType: UInt): Bool = { 169 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 170 } 171 172 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 173 174 def bindBackendParam(param: BackendParams): Unit = { 175 backendParam = param 176 } 177 178 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 179 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 180 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 181 if (this.isIQWakeUpSource) 182 require(!this.hasUncertainLatency, s"${this.name} is IQ wake up source, but has UncertainLatency") 183 } 184 185 def updateExuIdx(idx: Int): Unit = { 186 this.exuIdx = idx 187 } 188 189 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 190 191 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 192 193 def getIntWBPort = { 194 wbPortConfigs.collectFirst { 195 case x: IntWB => x 196 } 197 } 198 199 def getVfWBPort = { 200 wbPortConfigs.collectFirst { 201 case x: VfWB => x 202 } 203 } 204 205 /** 206 * Get the [[DataConfig]] that this exu need to read 207 */ 208 def pregRdDataCfgSet: Set[DataConfig] = { 209 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 210 } 211 212 /** 213 * Get the [[DataConfig]] that this exu need to write 214 */ 215 def pregWbDataCfgSet: Set[DataConfig] = { 216 this.wbPortConfigs.map(_.dataCfg).toSet 217 } 218 219 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 220 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 221 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 222 223 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 224 225 exuSrcsCfgSet 226 } 227 228 /** 229 * Get the [[DataConfig]] mapped indices of source data of exu 230 * 231 * @example 232 * {{{ 233 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 234 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 235 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 236 * getRfReadSrcIdx(VConfigData()) = Seq(4) 237 * }}} 238 * @return Map[DataConfig -> Seq[indices]] 239 */ 240 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 241 val dataCfgs = DataConfig.RegSrcDataSet 242 val rfRdDataCfgSet = this.getRfReadDataCfgSet 243 dataCfgs.toSeq.map { cfg => 244 ( 245 cfg, 246 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 247 if (set.contains(cfg)) 248 Option(srcIdx) 249 else 250 None 251 }.filter(_.nonEmpty).map(_.get) 252 ) 253 }.toMap 254 } 255 256 def genExuModule(implicit p: Parameters): ExeUnit = { 257 new ExeUnit(this) 258 } 259 260 def genExuInputBundle(implicit p: Parameters): ExuInput = { 261 new ExuInput(this) 262 } 263 264 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 265 new ExuOutput(this) 266 } 267 268 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 269 new ExuBypassBundle(this) 270 } 271} 272