1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB, FpWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val readVfRf: Boolean = numVfSrc > 0 46 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 47 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 48 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 49 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 50 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 51 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 52 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 53 val writeVfRf: Boolean = writeVecRf 54 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 55 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 56 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 57 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 58 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 59 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 60 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 61 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 62 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 63 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 64 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 65 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 66 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 67 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 68 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 69 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 70 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 71 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 72 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 73 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 74 75 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 76 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 77 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 78 79 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 80 81 def copyNum: Int = { 82 val setIQ = mutable.Set[IssueBlockParams]() 83 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 84 backendParam.allIssueParams.map{ issueParams => 85 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 86 setIQ.add(issueParams) 87 } 88 } 89 } 90 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 91 1 + setIQ.size / copyDistance 92 } 93 def rdPregIdxWidth: Int = { 94 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 95 } 96 97 def wbPregIdxWidth: Int = { 98 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 99 } 100 101 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 102 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 103 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 104 105 /** 106 * Check if this exu has certain latency 107 */ 108 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 109 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 110 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 111 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 112 // only load use it 113 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 114 115 /** 116 * Get mapping from FuType to Latency value. 117 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 118 * 119 * @return Map[ [[BigInt]], Latency] 120 */ 121 def fuLatencyMap: Map[FuType.OHType, Int] = { 122 if (latencyCertain) 123 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 124 else if (hasUncertainLatencyVal) 125 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 126 else 127 Map() 128 } 129 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 130 if (latencyCertain) 131 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 132 else if (hasUncertainLatencyVal) 133 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 134 else 135 Map() 136 } 137 138 /** 139 * Get set of latency of function units. 140 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 141 * 142 * @return Set[Latency] 143 */ 144 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 145 146 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 147 148 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 149 150 def intFuLatencyMap: Map[FuType.OHType, Int] = { 151 if (intLatencyCertain) { 152 if (isVfExeUnit) { 153 // vf exe unit writing back to int regfile should delay 1 cycle 154 // vf exe unit need og2 --> delay 1 cycle 155 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 156 } else { 157 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 158 } 159 } 160 else 161 Map() 162 } 163 164 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 165 166 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 167 if (fpLatencyCertain) 168 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 169 else 170 Map() 171 } 172 173 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 174 175 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 176 if (vfLatencyCertain) 177 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 178 else 179 Map() 180 } 181 182 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 183 184 /** 185 * Check if this exu has fixed latency 186 */ 187 def isFixedLatency: Boolean = { 188 if (latencyCertain) 189 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 190 false 191 } 192 193 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 194 195 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 196 197 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 198 199 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 200 201 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 202 203 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 204 205 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 206 207 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 208 209 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 210 211 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 212 213 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 214 215 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 216 217 def hasLoadExu = hasLoadFu || hasHyldaFu 218 219 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 220 221 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 222 223 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 224 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 225 } 226 227 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 228 229 def getWBSource: SchedulerType = { 230 schdType 231 } 232 233 def hasCrossWb: Boolean = { 234 schdType match { 235 case IntScheduler() => writeFpRf || writeVecRf 236 case VfScheduler() => writeIntRf 237 case _ => false 238 } 239 } 240 241 def canAccept(fuType: UInt): Bool = { 242 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 243 } 244 245 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 246 247 def bindBackendParam(param: BackendParams): Unit = { 248 backendParam = param 249 } 250 251 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 252 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 253 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 254 if (this.isIQWakeUpSource) { 255 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 256 } 257 } 258 259 def updateExuIdx(idx: Int): Unit = { 260 this.exuIdx = idx 261 } 262 263 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 264 265 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 266 267 def getIntWBPort = { 268 wbPortConfigs.collectFirst { 269 case x: IntWB => x 270 } 271 } 272 273 def getFpWBPort = { 274 wbPortConfigs.collectFirst { 275 case x: FpWB => x 276 } 277 } 278 279 def getVfWBPort = { 280 wbPortConfigs.collectFirst { 281 case x: VfWB => x 282 } 283 } 284 285 /** 286 * Get the [[DataConfig]] that this exu need to read 287 */ 288 def pregRdDataCfgSet: Set[DataConfig] = { 289 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 290 } 291 292 /** 293 * Get the [[DataConfig]] that this exu need to write 294 */ 295 def pregWbDataCfgSet: Set[DataConfig] = { 296 this.wbPortConfigs.map(_.dataCfg).toSet 297 } 298 299 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 300 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 301 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 302 303 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 304 305 exuSrcsCfgSet 306 } 307 308 /** 309 * Get the [[DataConfig]] mapped indices of source data of exu 310 * 311 * @example 312 * {{{ 313 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 314 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 315 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 316 * getRfReadSrcIdx(VConfigData()) = Seq(4) 317 * }}} 318 * @return Map[DataConfig -> Seq[indices]] 319 */ 320 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 321 val dataCfgs = DataConfig.RegSrcDataSet 322 val rfRdDataCfgSet = this.getRfReadDataCfgSet 323 dataCfgs.toSeq.map { cfg => 324 ( 325 cfg, 326 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 327 if (set.contains(cfg)) 328 Option(srcIdx) 329 else 330 None 331 }.filter(_.nonEmpty).map(_.get) 332 ) 333 }.toMap 334 } 335 336 def genExuModule(implicit p: Parameters): ExeUnit = { 337 new ExeUnit(this) 338 } 339 340 def genExuInputBundle(implicit p: Parameters): ExuInput = { 341 new ExuInput(this) 342 } 343 344 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 345 new ExuOutput(this) 346 } 347 348 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 349 new ExuBypassBundle(this) 350 } 351} 352