1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB, FpWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val readVfRf: Boolean = numVfSrc > 0 46 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 47 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 48 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 49 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 50 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 51 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 52 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 53 val writeVfRf: Boolean = writeVecRf 54 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 55 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 56 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 57 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 58 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 59 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 60 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 61 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 62 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 63 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 64 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 65 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 66 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 67 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 68 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 69 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 70 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 71 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 72 val writeVConfig: Boolean = fuConfigs.map(_.writeVConfig).reduce(_ || _) 73 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 74 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 75 76 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 77 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 78 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 79 80 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 81 82 def copyNum: Int = { 83 val setIQ = mutable.Set[IssueBlockParams]() 84 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 85 backendParam.allIssueParams.map{ issueParams => 86 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 87 setIQ.add(issueParams) 88 } 89 } 90 } 91 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 92 1 + setIQ.size / copyDistance 93 } 94 def rdPregIdxWidth: Int = { 95 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 96 } 97 98 def wbPregIdxWidth: Int = { 99 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 100 } 101 102 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 103 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 104 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 105 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 106 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 107 108 /** 109 * Check if this exu has certain latency 110 */ 111 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 112 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 113 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 114 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 115 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 116 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 117 // only load use it 118 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 119 120 /** 121 * Get mapping from FuType to Latency value. 122 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 123 * 124 * @return Map[ [[BigInt]], Latency] 125 */ 126 def fuLatencyMap: Map[FuType.OHType, Int] = { 127 if (latencyCertain) 128 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 129 else if (hasUncertainLatencyVal) 130 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 131 else 132 Map() 133 } 134 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 135 if (latencyCertain) 136 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 137 else if (hasUncertainLatencyVal) 138 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 139 else 140 Map() 141 } 142 143 /** 144 * Get set of latency of function units. 145 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 146 * 147 * @return Set[Latency] 148 */ 149 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 150 151 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 152 153 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 154 155 def intFuLatencyMap: Map[FuType.OHType, Int] = { 156 if (intLatencyCertain) { 157 if (isVfExeUnit) { 158 // vf exe unit writing back to int regfile should delay 1 cycle 159 // vf exe unit need og2 --> delay 1 cycle 160 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 161 } else { 162 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 163 } 164 } 165 else 166 Map() 167 } 168 169 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 170 171 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 172 if (fpLatencyCertain) 173 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 174 else 175 Map() 176 } 177 178 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 179 180 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 181 if (vfLatencyCertain) 182 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 183 else 184 Map() 185 } 186 187 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 188 189 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 190 if (v0LatencyCertain) 191 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 192 else 193 Map() 194 } 195 196 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 197 198 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 199 if (vlLatencyCertain) 200 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 201 else 202 Map() 203 } 204 205 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 206 207 /** 208 * Check if this exu has fixed latency 209 */ 210 def isFixedLatency: Boolean = { 211 if (latencyCertain) 212 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 213 false 214 } 215 216 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 217 218 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 219 220 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 221 222 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 223 224 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 225 226 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 227 228 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 229 230 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 231 232 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 233 234 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 235 236 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 237 238 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 239 240 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 241 242 def hasLoadExu = hasLoadFu || hasHyldaFu 243 244 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 245 246 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 247 248 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 249 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 250 } 251 252 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 253 254 def getWBSource: SchedulerType = { 255 schdType 256 } 257 258 def hasCrossWb: Boolean = { 259 schdType match { 260 case IntScheduler() => writeFpRf || writeVecRf 261 case VfScheduler() => writeIntRf 262 case _ => false 263 } 264 } 265 266 def canAccept(fuType: UInt): Bool = { 267 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 268 } 269 270 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 271 272 def bindBackendParam(param: BackendParams): Unit = { 273 backendParam = param 274 } 275 276 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 277 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 278 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 279 if (this.isIQWakeUpSource) { 280 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 281 } 282 } 283 284 def updateExuIdx(idx: Int): Unit = { 285 this.exuIdx = idx 286 } 287 288 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 289 290 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 291 292 def getIntWBPort = { 293 wbPortConfigs.collectFirst { 294 case x: IntWB => x 295 } 296 } 297 298 def getFpWBPort = { 299 wbPortConfigs.collectFirst { 300 case x: FpWB => x 301 } 302 } 303 304 def getVfWBPort = { 305 wbPortConfigs.collectFirst { 306 case x: VfWB => x 307 } 308 } 309 310 /** 311 * Get the [[DataConfig]] that this exu need to read 312 */ 313 def pregRdDataCfgSet: Set[DataConfig] = { 314 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 315 } 316 317 /** 318 * Get the [[DataConfig]] that this exu need to write 319 */ 320 def pregWbDataCfgSet: Set[DataConfig] = { 321 this.wbPortConfigs.map(_.dataCfg).toSet 322 } 323 324 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 325 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 326 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 327 328 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 329 330 exuSrcsCfgSet 331 } 332 333 /** 334 * Get the [[DataConfig]] mapped indices of source data of exu 335 * 336 * @example 337 * {{{ 338 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 339 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 340 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 341 * getRfReadSrcIdx(VConfigData()) = Seq(4) 342 * }}} 343 * @return Map[DataConfig -> Seq[indices]] 344 */ 345 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 346 val dataCfgs = DataConfig.RegSrcDataSet 347 val rfRdDataCfgSet = this.getRfReadDataCfgSet 348 dataCfgs.toSeq.map { cfg => 349 ( 350 cfg, 351 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 352 if (set.contains(cfg)) 353 Option(srcIdx) 354 else 355 None 356 }.filter(_.nonEmpty).map(_.get) 357 ) 358 }.toMap 359 } 360 361 def genExuModule(implicit p: Parameters): ExeUnit = { 362 new ExeUnit(this) 363 } 364 365 def genExuInputBundle(implicit p: Parameters): ExuInput = { 366 new ExuInput(this) 367 } 368 369 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 370 new ExuOutput(this) 371 } 372 373 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 374 new ExuBypassBundle(this) 375 } 376} 377