1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[PregWB], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 // used in bypass to select data of exu output 28 var exuIdx: Int = -1 29 var backendParam: BackendParams = null 30 31 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 32 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 33 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 34 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 35 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 36 val numSrc: Int = fuConfigs.map(_.numSrc).max 37 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 38 val readIntRf: Boolean = numIntSrc > 0 39 val readFpRf: Boolean = numFpSrc > 0 40 val readVecRf: Boolean = numVecSrc > 0 41 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 42 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 43 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 44 val writeVfRf: Boolean = writeFpRf || writeVecRf 45 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 46 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 47 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 48 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 49 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 50 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 51 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 52 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 53 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 54 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 55 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 56 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 57 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 58 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 59 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 60 61 def rdPregIdxWidth: Int = { 62 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 63 } 64 65 def wbPregIdxWidth: Int = { 66 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 67 } 68 69 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 70 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 71 72 /** 73 * Check if this exu has certain latency 74 */ 75 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 76 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 77 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 78 79 /** 80 * Get mapping from FuType to Latency value. 81 * If [[latencyCertain]] is false, get empty [[Map]] 82 * 83 * @return Map[FuType, Latency] 84 */ 85 def fuLatencyMap: Map[Int, Int] = { 86 if (latencyCertain) 87 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 88 else 89 Map() 90 } 91 92 /** 93 * Get set of latency of function units. 94 * If [[latencyCertain]] is false, get empty [[Set]] 95 * 96 * @return Set[Latency] 97 */ 98 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 99 100 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 101 102 def intFuLatencyMap: Map[Int, Int] = { 103 if (intLatencyCertain) 104 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 105 else 106 Map() 107 } 108 109 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 110 111 def vfFuLatencyMap: Map[Int, Int] = { 112 if (vfLatencyCertain) 113 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 114 else 115 Map() 116 } 117 118 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 119 120 /** 121 * Check if this exu has fixed latency 122 */ 123 def isFixedLatency: Boolean = { 124 if (latencyCertain) 125 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 126 false 127 } 128 129 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 130 131 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 132 133 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 134 135 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 136 137 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 138 139 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 140 141 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 142 143 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 144 145 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 146 147 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 148 149 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 150 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 151 } 152 153 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 154 155 def getWBSource: SchedulerType = { 156 schdType 157 } 158 159 def hasCrossWb: Boolean = { 160 schdType match { 161 case IntScheduler() => writeFpRf || writeVecRf 162 case VfScheduler() => writeIntRf 163 case _ => false 164 } 165 } 166 167 def canAccept(fuType: UInt): Bool = { 168 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 169 } 170 171 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 172 173 def bindBackendParam(param: BackendParams): Unit = { 174 backendParam = param 175 } 176 177 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 178 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 179 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 180 if (this.isIQWakeUpSource) 181 require(!this.hasUncertainLatency, s"${this.name} is IQ wake up source, but has UncertainLatency") 182 } 183 184 def updateExuIdx(idx: Int): Unit = { 185 this.exuIdx = idx 186 } 187 188 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 189 190 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 191 192 def getIntWBPort = { 193 wbPortConfigs.collectFirst { 194 case x: IntWB => x 195 } 196 } 197 198 def getVfWBPort = { 199 wbPortConfigs.collectFirst { 200 case x: VfWB => x 201 } 202 } 203 204 /** 205 * Get the [[DataConfig]] that this exu need to read 206 */ 207 def pregRdDataCfgSet: Set[DataConfig] = { 208 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 209 } 210 211 /** 212 * Get the [[DataConfig]] that this exu need to write 213 */ 214 def pregWbDataCfgSet: Set[DataConfig] = { 215 this.wbPortConfigs.map(_.dataCfg).toSet 216 } 217 218 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 219 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 220 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 221 222 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 223 224 exuSrcsCfgSet 225 } 226 227 /** 228 * Get the [[DataConfig]] mapped indices of source data of exu 229 * 230 * @example 231 * {{{ 232 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 233 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 234 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 235 * getRfReadSrcIdx(VConfigData()) = Seq(4) 236 * }}} 237 * @return Map[DataConfig -> Seq[indices]] 238 */ 239 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 240 val dataCfgs = DataConfig.RegSrcDataSet 241 val rfRdDataCfgSet = this.getRfReadDataCfgSet 242 dataCfgs.toSeq.map { cfg => 243 ( 244 cfg, 245 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 246 if (set.contains(cfg)) 247 Option(srcIdx) 248 else 249 None 250 }.filter(_.nonEmpty).map(_.get) 251 ) 252 }.toMap 253 } 254 255 def genExuModule(implicit p: Parameters): ExeUnit = { 256 new ExeUnit(this) 257 } 258 259 def genExuInputBundle(implicit p: Parameters): ExuInput = { 260 new ExuInput(this) 261 } 262 263 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 264 new ExuOutput(this) 265 } 266 267 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 268 new ExuBypassBundle(this) 269 } 270} 271