1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 40 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 41 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 42 val numSrc: Int = fuConfigs.map(_.numSrc).max 43 val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max 44 val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max 45 val readIntRf: Boolean = numIntSrc > 0 46 val readFpRf: Boolean = numFpSrc > 0 47 val readVecRf: Boolean = numVecSrc > 0 48 val readVfRf: Boolean = numVfSrc > 0 49 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 50 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 51 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 52 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 53 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 54 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 55 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 56 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 57 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 58 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 59 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 60 val writeVfRf: Boolean = writeVecRf 61 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 62 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 63 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 64 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 65 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 66 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 67 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 68 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 69 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 70 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 71 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 72 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 73 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 74 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 75 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 76 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 77 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 78 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 79 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 80 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 81 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 82 83 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 84 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 85 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 86 87 // exu writeback: 0 normalout; 1 intout; 2 fpout; 3 vecout 88 val wbNeedIntWen : Boolean = writeIntRf && !isMemExeUnit 89 val wbNeedFpWen : Boolean = writeFpRf && !isMemExeUnit 90 val wbNeedVecWen : Boolean = writeVecRf && !isMemExeUnit 91 val wbNeedV0Wen : Boolean = writeV0Rf && !isMemExeUnit 92 val wbNeedVlWen : Boolean = writeVlRf && !isMemExeUnit 93 val wbPathNum: Int = Seq(wbNeedIntWen, wbNeedFpWen, wbNeedVecWen, wbNeedV0Wen, wbNeedVlWen).count(_ == true) + 1 94 val wbNeeds = Seq( 95 ("int", wbNeedIntWen), 96 ("fp", wbNeedFpWen), 97 ("vec", wbNeedVecWen), 98 ("v0", wbNeedV0Wen), 99 ("vl", wbNeedVlWen) 100 ) 101 val wbIndexeds = wbNeeds.filter(_._2).zipWithIndex.map { 102 case ((label, _), index) => (label, index + 1) 103 }.toMap 104 val wbIntIndex: Int = wbIndexeds.getOrElse("int", 0) 105 val wbFpIndex : Int = wbIndexeds.getOrElse("fp", 0) 106 val wbVecIndex: Int = wbIndexeds.getOrElse("vec", 0) 107 val wbV0Index : Int = wbIndexeds.getOrElse("v0" , 0) 108 val wbVlIndex : Int = wbIndexeds.getOrElse("vl" , 0) 109 val wbIndex: Seq[Int] = Seq(wbIntIndex, wbFpIndex, wbVecIndex, wbV0Index, wbVlIndex) 110 111 112 113 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 114 115 def copyNum: Int = { 116 val setIQ = mutable.Set[IssueBlockParams]() 117 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 118 backendParam.allIssueParams.map{ issueParams => 119 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 120 setIQ.add(issueParams) 121 } 122 } 123 } 124 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 125 1 + setIQ.size / copyDistance 126 } 127 def rdPregIdxWidth: Int = { 128 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 129 } 130 131 def wbPregIdxWidth: Int = { 132 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 133 } 134 135 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 136 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 137 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 138 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 139 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 140 141 /** 142 * Check if this exu has certain latency 143 */ 144 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 145 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 146 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 147 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 148 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 149 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 150 // only load use it 151 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 152 153 /** 154 * Get mapping from FuType to Latency value. 155 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 156 * 157 * @return Map[ [[BigInt]], Latency] 158 */ 159 def fuLatencyMap: Map[FuType.OHType, Int] = { 160 if (latencyCertain) 161 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 162 else if (hasUncertainLatencyVal) 163 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 164 else 165 Map() 166 } 167 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 168 if (latencyCertain) 169 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 170 else if (hasUncertainLatencyVal) 171 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 172 else 173 Map() 174 } 175 176 /** 177 * Get set of latency of function units. 178 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 179 * 180 * @return Set[Latency] 181 */ 182 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 183 184 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 185 186 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 187 188 def intFuLatencyMap: Map[FuType.OHType, Int] = { 189 if (intLatencyCertain) { 190 if (isVfExeUnit) { 191 // vf exe unit writing back to int regfile should delay 1 cycle 192 // vf exe unit need og2 --> delay 1 cycle 193 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 194 } else { 195 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 196 } 197 } 198 else 199 Map() 200 } 201 202 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 203 204 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 205 if (fpLatencyCertain) 206 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 207 else 208 Map() 209 } 210 211 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 212 213 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 214 if (vfLatencyCertain) 215 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 216 else 217 Map() 218 } 219 220 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 221 222 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 223 if (v0LatencyCertain) 224 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 225 else 226 Map() 227 } 228 229 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 230 231 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 232 if (vlLatencyCertain) 233 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 234 else 235 Map() 236 } 237 238 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 239 240 /** 241 * Check if this exu has fixed latency 242 */ 243 def isFixedLatency: Boolean = { 244 if (latencyCertain) 245 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 246 false 247 } 248 249 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 250 251 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 252 253 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 254 255 def hasi2vFu = fuConfigs.map(_.fuType == FuType.i2v).reduce(_ || _) 256 257 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 258 259 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 260 261 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 262 263 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 264 265 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 266 267 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 268 269 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 270 271 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 272 273 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 274 275 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 276 277 def hasLoadExu = hasLoadFu || hasHyldaFu 278 279 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 280 281 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 282 283 def CanCompress = !hasBrhFu || (hasBrhFu && hasi2vFu) 284 285 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 286 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 287 } 288 289 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 290 291 def getWBSource: SchedulerType = { 292 schdType 293 } 294 295 def hasCrossWb: Boolean = { 296 schdType match { 297 case IntScheduler() => writeFpRf || writeVecRf 298 case VfScheduler() => writeIntRf 299 case _ => false 300 } 301 } 302 303 def canAccept(fuType: UInt): Bool = { 304 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 305 } 306 307 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 308 309 def bindBackendParam(param: BackendParams): Unit = { 310 backendParam = param 311 } 312 313 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 314 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 315 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 316 if (this.isIQWakeUpSource) { 317 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 318 } 319 } 320 321 def updateExuIdx(idx: Int): Unit = { 322 this.exuIdx = idx 323 } 324 325 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 326 327 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 328 329 def getIntWBPort = { 330 wbPortConfigs.collectFirst { 331 case x: IntWB => x 332 } 333 } 334 335 def getFpWBPort = { 336 wbPortConfigs.collectFirst { 337 case x: FpWB => x 338 } 339 } 340 341 def getVfWBPort = { 342 wbPortConfigs.collectFirst { 343 case x: VfWB => x 344 } 345 } 346 347 def getV0WBPort = { 348 wbPortConfigs.collectFirst { 349 case x: V0WB => x 350 } 351 } 352 353 def getVlWBPort = { 354 wbPortConfigs.collectFirst { 355 case x: VlWB => x 356 } 357 } 358 359 /** 360 * Get the [[DataConfig]] that this exu need to read 361 */ 362 def pregRdDataCfgSet: Set[DataConfig] = { 363 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 364 } 365 366 /** 367 * Get the [[DataConfig]] that this exu need to write 368 */ 369 def pregWbDataCfgSet: Set[DataConfig] = { 370 this.wbPortConfigs.map(_.dataCfg).toSet 371 } 372 373 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 374 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 375 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 376 377 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 378 379 exuSrcsCfgSet 380 } 381 382 /** 383 * Get the [[DataConfig]] mapped indices of source data of exu 384 * 385 * @example 386 * {{{ 387 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 388 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 389 * getRfReadSrcIdx(V0Data()) = Seq(3) 390 * getRfReadSrcIdx(VlData()) = Seq(4) 391 * }}} 392 * @return Map[DataConfig -> Seq[indices]] 393 */ 394 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 395 val dataCfgs = DataConfig.RegSrcDataSet 396 val rfRdDataCfgSet = this.getRfReadDataCfgSet 397 dataCfgs.toSeq.map { cfg => 398 ( 399 cfg, 400 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 401 if (set.contains(cfg)) 402 Option(srcIdx) 403 else 404 None 405 }.filter(_.nonEmpty).map(_.get) 406 ) 407 }.toMap 408 } 409 410 def genExuModule(implicit p: Parameters): ExeUnit = { 411 new ExeUnit(this) 412 } 413 414 def genExuInputBundle(implicit p: Parameters): ExuInput = { 415 new ExuInput(this) 416 } 417 418 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 419 new ExuOutput(this) 420 } 421 422 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 423 new ExuBypassBundle(this) 424 } 425} 426