1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.experimental.hierarchy.{Definition, instantiable} 23import chisel3.util._ 24import utils._ 25import utility._ 26import xiangshan._ 27import xiangshan.backend.fu.fpu.{FMA, FPUSubModule} 28import xiangshan.backend.fu.{CSR, FUWithRedirect, Fence, FenceToSbuffer} 29 30class FenceIO(implicit p: Parameters) extends XSBundle { 31 val sfence = Output(new SfenceBundle) 32 val fencei = Output(Bool()) 33 val sbuffer = new FenceToSbuffer 34} 35 36@instantiable 37class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) { 38 39 val disableSfence = WireInit(false.B) 40 val disableHfenceg = WireInit(false.B) 41 val disableHfencev = WireInit(false.B) 42 val virtMode = WireInit(false.B) 43 val csr_frm = WireInit(frm.getOrElse(0.U(3.W))) 44 45 val hasRedirect = config.fuConfigs.zip(functionUnits).filter(_._1.hasRedirect).map(_._2) 46 println(s"${functionUnits} ${hasRedirect} hasRedirect: ${hasRedirect.length}") 47 if (hasRedirect.nonEmpty) { 48 require(hasRedirect.length <= 1) 49 io.out.bits.redirectValid := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOutValid 50 io.out.bits.redirect := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOut 51 } 52 53 if (config.fuConfigs.contains(csrCfg)) { 54 val csr = functionUnits.collectFirst{ 55 case c: CSR => c 56 }.get 57 csr.csrio <> csrio.get 58 csrio.get.tlb := DelayN(csr.csrio.tlb, 2) 59 csrio.get.customCtrl := DelayN(csr.csrio.customCtrl, 2) 60 csrio.get.trapTarget := RegNext(csr.csrio.trapTarget) 61 csr.csrio.exception := DelayN(csrio.get.exception, 2) 62 disableSfence := csr.csrio.disableSfence 63 disableHfenceg := csr.csrio.disableHfenceg 64 disableHfencev := csr.csrio.disableHfencev 65 virtMode := csr.csrio.customCtrl.virtMode 66 csr_frm := csr.csrio.fpu.frm 67 // setup skip for hpm CSR read 68 io.out.bits.debug.isPerfCnt := RegNext(csr.csrio.isPerfCnt) // TODO: this is dirty 69 } 70 71 if (config.fuConfigs.contains(fenceCfg)) { 72 val fence = functionUnits.collectFirst{ 73 case f: Fence => f 74 }.get 75 fenceio.get.sfence <> fence.sfence 76 fenceio.get.fencei <> fence.fencei 77 fenceio.get.sbuffer <> fence.toSbuffer 78 fence.io.out.ready := true.B 79 fence.disableSfence := disableSfence 80 fence.disableHfenceg := disableHfenceg 81 fence.disableHfencev := disableHfencev 82 fence.virtMode := virtMode 83 } 84 85 val fpModules = functionUnits.zip(config.fuConfigs.zipWithIndex).filter(_._1.isInstanceOf[FPUSubModule]) 86 if (fpModules.nonEmpty) { 87 // frm is from csr/frm (from CSR) or instr_rm (from instruction decoding) 88 val fpSubModules = fpModules.map(_._1.asInstanceOf[FPUSubModule]) 89 fpSubModules.foreach(mod => { 90 val instr_rm = mod.io.in.bits.uop.ctrl.fpu.rm 91 mod.rm := Mux(instr_rm =/= 7.U, instr_rm, csr_frm) 92 }) 93 // fflags is selected by arbSelReg 94 require(config.hasFastUopOut, "non-fast not implemented") 95 val fflagsSel = fpModules.map{ case (fu, (cfg, i)) => 96 val fflagsValid = arbSelReg(i) 97 val fflags = fu.asInstanceOf[FPUSubModule].fflags 98 val fflagsBits = if (cfg.fastImplemented) fflags else RegNext(fflags) 99 (fflagsValid, fflagsBits) 100 } 101 io.out.bits.fflags := Mux1H(fflagsSel.map(_._1), fflagsSel.map(_._2)) 102 } 103 104 val fmaModules = functionUnits.filter(_.isInstanceOf[FMA]).map(_.asInstanceOf[FMA]) 105 if (fmaModules.nonEmpty) { 106 require(fmaModules.length == 1) 107 fmaModules.head.midResult <> fmaMid.get 108 } 109 110 if (config.readIntRf) { 111 val in = io.fromInt 112 val out = io.out 113 XSDebug(in.valid, p"fromInt(${in.valid} ${in.ready}) toInt(${out.valid} ${out.ready})\n") 114 XSDebug(io.redirect.valid, p"Redirect:(${io.redirect.valid}) robIdx:${io.redirect.bits.robIdx}\n") 115 XSDebug(in.valid, p"src1:${Hexadecimal(in.bits.src(0))} src2:${Hexadecimal(in.bits.src(1))} " + 116 p"func:${Binary(in.bits.uop.ctrl.fuOpType)} pc:${Hexadecimal(in.bits.uop.cf.pc)} robIdx:${in.bits.uop.robIdx}\n") 117 XSDebug(out.valid, p"out res:${Hexadecimal(out.bits.data)} robIdx:${out.bits.uop.robIdx}\n") 118 } 119 120} 121 122class AluExeUnit(implicit p: Parameters) extends ExeUnit(AluExeUnitCfg) 123class JumpCSRExeUnit(implicit p: Parameters) extends ExeUnit(JumpCSRExeUnitCfg) 124class JumpExeUnit(implicit p: Parameters) extends ExeUnit(JumpExeUnitCfg) 125class StdExeUnit(implicit p: Parameters) extends ExeUnit(StdExeUnitCfg) 126class FmacExeUnit(implicit p: Parameters) extends ExeUnit(FmacExeUnitCfg) 127class FmiscExeUnit(implicit p: Parameters) extends ExeUnit(FmiscExeUnitCfg) 128 129object ExeUnitDef { 130 val defMap = new scala.collection.mutable.HashMap[ExuConfig, Definition[ExeUnit]]() 131 132 def apply(cfg: ExuConfig)(implicit p: Parameters): Definition[ExeUnit] = { 133 cfg match { 134 case JumpExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new JumpExeUnit)) 135 case AluExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new AluExeUnit)) 136 case MulDivExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new MulDivExeUnit)) 137 // TODO: CSR should also use instance. We need to fix difftest. 138 // We should not call DifftestModule in Definition/Instance for now. 139 case JumpCSRExeUnitCfg => Definition(new JumpCSRExeUnit) 140 case FmacExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new FmacExeUnit)) 141 case FmiscExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new FmiscExeUnit)) 142 case StdExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new StdExeUnit)) 143 case _ => { 144 println(s"cannot generate exeUnit from $cfg") 145 null 146 } 147 } 148 } 149} 150