1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility._ 25import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 26import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 27import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 28import xiangshan.backend.datapath.WbConfig.{PregWB, _} 29import xiangshan.backend.fu.FuType 30import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm} 31import xiangshan.backend.fu.fpu.Bundles.Frm 32import xiangshan.backend.fu.wrapper.{CSRInput, CSRToDecode} 33 34class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 35 val flush = Flipped(ValidIO(new Redirect())) 36 val in = Flipped(DecoupledIO(new ExuInput(params))) 37 val out = DecoupledIO(new ExuOutput(params)) 38 val csrin = Option.when(params.hasCSR)(new CSRInput) 39 val csrio = Option.when(params.hasCSR)(new CSRFileIO) 40 val csrToDecode = Option.when(params.hasCSR)(Output(new CSRToDecode)) 41 val fenceio = Option.when(params.hasFence)(new FenceIO) 42 val frm = Option.when(params.needSrcFrm)(Input(Frm())) 43 val vxrm = Option.when(params.needSrcVxrm)(Input(Vxrm())) 44 val vtype = Option.when(params.writeVConfig)((Valid(new VType))) 45 val vlIsZero = Option.when(params.writeVConfig)(Output(Bool())) 46 val vlIsVlmax = Option.when(params.writeVConfig)(Output(Bool())) 47} 48 49class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 50 override def shouldBeInlined: Boolean = false 51 52 lazy val module = new ExeUnitImp(this)(p, exuParams) 53} 54 55class ExeUnitImp( 56 override val wrapper: ExeUnit 57)(implicit 58 p: Parameters, exuParams: ExeUnitParams 59) extends LazyModuleImp(wrapper) with HasXSParameter{ 60 private val fuCfgs = exuParams.fuConfigs 61 62 val io = IO(new ExeUnitIO(exuParams)) 63 64 val funcUnits = fuCfgs.map(cfg => { 65 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 66 val module = cfg.fuGen(p, cfg) 67 module 68 }) 69 70 if (EnableClockGate) { 71 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 72 val clk_en = WireInit(false.B) 73 val fuVld_en = WireInit(false.B) 74 val fuVld_en_reg = RegInit(false.B) 75 val uncer_en_reg = RegInit(false.B) 76 77 def latReal: Int = cfg.latency.latencyVal.getOrElse(0) 78 def extralat: Int = cfg.latency.extraLatencyVal.getOrElse(0) 79 80 val uncerLat = cfg.latency.uncertainEnable.nonEmpty 81 val lat0 = (latReal == 0 && !uncerLat).asBool 82 val latN = (latReal > 0 && !uncerLat).asBool 83 84 val fuVldVec = (io.in.valid && latN) +: Seq.fill(latReal)(RegInit(false.B)) 85 val fuRdyVec = Seq.fill(latReal)(Wire(Bool())) :+ io.out.ready 86 87 for (i <- 0 until latReal) { 88 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 89 } 90 91 for (i <- 1 to latReal) { 92 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 93 fuVldVec(i) := fuVldVec(i - 1) 94 }.elsewhen(fuRdyVec(i)) { 95 fuVldVec(i) := false.B 96 } 97 } 98 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 99 fuVld_en_reg := fuVld_en 100 101 when(uncerLat.asBool && io.in.fire) { 102 uncer_en_reg := true.B 103 }.elsewhen(uncerLat.asBool && io.out.fire) { 104 uncer_en_reg := false.B 105 } 106 107 when(lat0 && io.in.fire) { 108 clk_en := true.B 109 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 110 clk_en := true.B 111 }.elsewhen(uncerLat.asBool && io.in.fire || uncer_en_reg) { 112 clk_en := true.B 113 } 114 115 if (cfg.ckAlwaysEn) { 116 clk_en := true.B 117 } 118 119 fu.clock := ClockGate(false.B, clk_en, clock) 120 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 121 } 122 } 123 124 val busy = RegInit(false.B) 125 if (exuParams.latencyCertain){ 126 busy := false.B 127 } 128 else { 129 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 130 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 131 busy := false.B 132 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 133 busy := false.B 134 }.elsewhen(io.out.fire) { 135 busy := false.B 136 }.elsewhen(io.in.fire) { 137 busy := true.B 138 } 139 } 140 141 exuParams.wbPortConfigs.map{ 142 x => x match { 143 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 144 s"${exuParams.name}: WbPort must priority=0 or priority=1") 145 case FpWB(port, priority) => assert(priority >= 0 && priority <= 2, 146 s"${exuParams.name}: WbPort must priority=0 or priority=1") 147 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 148 s"${exuParams.name}: WbPort must priority=0 or priority=1") 149 case _ => 150 } 151 } 152 val intWbPort = exuParams.getIntWBPort 153 if (intWbPort.isDefined){ 154 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 155 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 156 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 157 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 158 samePort.wbPortConfigs.map( 159 x => x match { 160 case IntWB(port, priority) => { 161 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 162 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 163 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 164 } 165 case _ => 166 } 167 ) 168 ) 169 } 170 val fpWbPort = exuParams.getFpWBPort 171 if (fpWbPort.isDefined) { 172 val sameFpPortExuParam = backendParams.allExuParams.filter(_.getFpWBPort.isDefined) 173 .filter(_.getFpWBPort.get.port == fpWbPort.get.port) 174 val samePortOneCertainOneUncertain = sameFpPortExuParam.map(_.latencyCertain).contains(true) && sameFpPortExuParam.map(_.latencyCertain).contains(false) 175 if (samePortOneCertainOneUncertain) sameFpPortExuParam.map(samePort => 176 samePort.wbPortConfigs.map( 177 x => x match { 178 case FpWB(port, priority) => { 179 if (!samePort.latencyCertain) assert(priority == sameFpPortExuParam.size - 1, 180 s"${samePort.name}: FpWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameFpPortExuParam.size - 1})") 181 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 182 } 183 case _ => 184 } 185 ) 186 ) 187 } 188 val vfWbPort = exuParams.getVfWBPort 189 if (vfWbPort.isDefined) { 190 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 191 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 192 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 193 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 194 samePort.wbPortConfigs.map( 195 x => x match { 196 case VfWB(port, priority) => { 197 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 198 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 199 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 200 } 201 case _ => 202 } 203 ) 204 ) 205 } 206 if(backendParams.debugEn) { 207 dontTouch(io.out.ready) 208 } 209 // rob flush --> funcUnits 210 funcUnits.zipWithIndex.foreach { case (fu, i) => 211 fu.io.flush <> io.flush 212 } 213 214 def acceptCond(input: ExuInput): Seq[Bool] = { 215 input.params.fuConfigs.map(_.fuSel(input)) 216 } 217 218 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 219 220 // ExeUnit.in <---> Dispatcher.in 221 in1ToN.io.in.valid := io.in.valid && !busy 222 in1ToN.io.in.bits := io.in.bits 223 io.in.ready := !busy && in1ToN.io.in.ready 224 225 // Dispatcher.out <---> FunctionUnits 226 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 227 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 228 sink.valid := source.valid 229 source.ready := sink.ready 230 231 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 232 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 233 sink.bits.data.imm := source.bits.imm 234 sink.bits.ctrl.fuOpType := source.bits.fuOpType 235 sink.bits.ctrl.robIdx := source.bits.robIdx 236 sink.bits.ctrl.pdest := source.bits.pdest 237 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 238 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 239 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 240 sink.bits.ctrl.v0Wen .foreach(x => x := source.bits.v0Wen.get) 241 sink.bits.ctrl.vlWen .foreach(x => x := source.bits.vlWen.get) 242 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 243 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 244 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 245 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 246 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 247 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 248 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 249 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFpToVecInst := 0.U) 250 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP32Instr := 0.U) 251 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP64Instr := 0.U) 252 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 253 } 254 255 private val OutresVecs = funcUnits.map { fu => 256 def latDiff :Int = fu.cfg.latency.extraLatencyVal.getOrElse(0) 257 val OutresVec = fu.io.out.bits.res +: Seq.fill(latDiff)(Reg(chiselTypeOf(fu.io.out.bits.res))) 258 for (i <- 1 to latDiff) { 259 OutresVec(i) := OutresVec(i - 1) 260 } 261 OutresVec 262 } 263 OutresVecs.foreach(vec => vec.foreach(res =>dontTouch(res))) 264 265 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 266 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 267 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 268 private val fuOutresVec = OutresVecs.map(_.last) 269 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = fuOutresVec.map(_.redirect) 270 271 // Assume that one fu can only write int or fp or vec, 272 // otherwise, wenVec should be assigned to wen in fu. 273 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 274 private val fuFpWenVec = funcUnits.map( x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 275 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 276 private val fuV0WenVec = funcUnits.map(x => x.cfg.needV0Wen.B && x.io.out.bits.ctrl.v0Wen.getOrElse(false.B)) 277 private val fuVlWenVec = funcUnits.map(x => x.cfg.needVlWen.B && x.io.out.bits.ctrl.vlWen.getOrElse(false.B)) 278 // FunctionUnits <---> ExeUnit.out 279 280 private val outDataVec = Seq( 281 Some(fuOutresVec.map(_.data)), 282 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 283 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuout) => fuout.data}), 284 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 285 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuout) => fuout.data}), 286 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 287 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuout) => fuout.data}), 288 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 289 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuout) => fuout.data}), 290 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 291 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuout) => fuout.data}), 292 ).flatten 293 private val outDataValidOH = Seq( 294 Some(fuOutValidOH), 295 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 296 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuoutOH) => fuoutOH}), 297 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 298 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuoutOH) => fuoutOH}), 299 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 300 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuoutOH) => fuoutOH}), 301 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 302 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuoutOH) => fuoutOH}), 303 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 304 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuoutOH) => fuoutOH}), 305 ).flatten 306 307 io.out.valid := Cat(fuOutValidOH).orR 308 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 309 310 // select one fu's result 311 io.out.bits.data := VecInit(outDataVec.zip(outDataValidOH).map{ case(data, validOH) => Mux1H(validOH, data)}) 312 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 313 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 314 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 315 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 316 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 317 io.out.bits.v0Wen.foreach(x => x := Mux1H(fuOutValidOH, fuV0WenVec)) 318 io.out.bits.vlWen.foreach(x => x := Mux1H(fuOutValidOH, fuVlWenVec)) 319 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 320 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 321 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 322 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 323 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 324 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 325 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 326 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 327 328 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 329 fuio => 330 exuio <> fuio 331 fuio.exception := DelayN(exuio.exception, 2) 332 })) 333 io.csrin.foreach(exuio => funcUnits.foreach(fu => fu.io.csrin.foreach{fuio => fuio := exuio})) 334 io.csrToDecode.foreach(toDecode => funcUnits.foreach(fu => fu.io.csrToDecode.foreach(fuOut => toDecode := fuOut))) 335 336 io.vtype.foreach(exuio => funcUnits.foreach(fu => fu.io.vtype.foreach(fuio => exuio := fuio))) 337 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 338 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 339 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 340 io.vlIsZero.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsZero.foreach(fuio => exuio := fuio))) 341 io.vlIsVlmax.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsVlmax.foreach(fuio => exuio := fuio))) 342 343 // debug info 344 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 345 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 346 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 347} 348 349class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 350 val in = Flipped(DecoupledIO(gen)) 351 352 val out = Vec(n, DecoupledIO(gen)) 353} 354 355class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 356 (implicit p: Parameters) 357 extends Module { 358 359 val io = IO(new DispatcherIO(gen, n)) 360 361 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 362 363 XSError(io.in.valid && PopCount(acceptVec) > 1.U, p"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 364 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 365 366 io.out.zipWithIndex.foreach { case (out, i) => 367 out.valid := acceptVec(i) && io.in.valid 368 out.bits := io.in.bits 369 } 370 371 io.in.ready := Cat(io.out.map(_.ready)).andR 372} 373 374class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 375 val flush = Flipped(ValidIO(new Redirect())) 376 val in = Flipped(DecoupledIO(new MemExuInput())) 377 val out = DecoupledIO(new MemExuOutput()) 378} 379 380class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 381 val io = IO(new MemExeUnitIO) 382 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 383 fu.io.flush := io.flush 384 fu.io.in.valid := io.in.valid 385 io.in.ready := fu.io.in.ready 386 387 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 388 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 389 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 390 fu.io.in.bits.data.imm := io.in.bits.uop.imm 391 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 392 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 393 394 io.out.valid := fu.io.out.valid 395 fu.io.out.ready := io.out.ready 396 397 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 398 io.out.bits.data := fu.io.out.bits.res.data 399 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 400 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 401 io.out.bits.uop.fuType := io.in.bits.uop.fuType 402 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 403 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 404 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 405 406 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 407}