1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.DelayN 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30import xiangshan.backend.fu.FuType 31 32class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 33 val flush = Flipped(ValidIO(new Redirect())) 34 val in = Flipped(DecoupledIO(new ExuInput(params))) 35 val out = DecoupledIO(new ExuOutput(params)) 36 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 37 val fenceio = if (params.hasFence) Some(new FenceIO) else None 38 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 39 val vxrm = if (params.needSrcVxrm) Some(Input(UInt(2.W))) else None 40} 41 42class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 43 override def shouldBeInlined: Boolean = false 44 45 lazy val module = new ExeUnitImp(this)(p, exuParams) 46} 47 48class ExeUnitImp( 49 override val wrapper: ExeUnit 50)(implicit 51 p: Parameters, exuParams: ExeUnitParams 52) extends LazyModuleImp(wrapper) with HasXSParameter{ 53 private val fuCfgs = exuParams.fuConfigs 54 55 val io = IO(new ExeUnitIO(exuParams)) 56 57 val funcUnits = fuCfgs.map(cfg => { 58 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 59 val module = cfg.fuGen(p, cfg) 60 module 61 }) 62 63 if (EnableClockGate) { 64 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 65 val clk_en = WireInit(false.B) 66 val fuVld_en = WireInit(false.B) 67 val fuVld_en_reg = RegInit(false.B) 68 val uncer_en_reg = RegInit(false.B) 69 70 val lat0 = FuType.isLat0(io.in.bits.fuType) 71 val latN = FuType.isLatN(io.in.bits.fuType) 72 val uncerLat = FuType.isUncerLat(io.in.bits.fuType) 73 74 def lat: Int = cfg.latency.latencyVal.getOrElse(0) 75 76 val fuVldVec = (io.in.valid && latN) +: Seq.fill(lat)(RegInit(false.B)) 77 val fuRdyVec = Seq.fill(lat)(Wire(Bool())) :+ io.out.ready 78 79 for (i <- 0 until lat) { 80 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 81 } 82 83 for (i <- 1 to lat) { 84 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 85 fuVldVec(i) := fuVldVec(i - 1) 86 }.elsewhen(fuRdyVec(i)) { 87 fuVldVec(i) := false.B 88 } 89 } 90 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 91 fuVld_en_reg := fuVld_en 92 93 when(uncerLat && io.in.fire) { 94 uncer_en_reg := true.B 95 }.elsewhen(uncerLat && io.out.fire) { 96 uncer_en_reg := false.B 97 } 98 99 when(lat0 && io.in.fire) { 100 clk_en := true.B 101 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 102 clk_en := true.B 103 }.elsewhen(uncerLat && io.in.fire || uncer_en_reg) { 104 clk_en := true.B 105 } 106 107 if (cfg.ckAlwaysEn) { 108 clk_en := true.B 109 } 110 111 val clk_gate = Module(new ClockGate) 112 clk_gate.io.TE := false.B 113 clk_gate.io.E := clk_en 114 clk_gate.io.CK := clock 115 fu.clock := clk_gate.io.Q 116 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 117 } 118 } 119 120 val busy = RegInit(false.B) 121 if (exuParams.latencyCertain){ 122 busy := false.B 123 } 124 else { 125 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 126 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 127 busy := false.B 128 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 129 busy := false.B 130 }.elsewhen(io.out.fire) { 131 busy := false.B 132 }.elsewhen(io.in.fire) { 133 busy := true.B 134 } 135 } 136 137 exuParams.wbPortConfigs.map{ 138 x => x match { 139 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 140 s"${exuParams.name}: WbPort must priority=0 or priority=1") 141 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 142 s"${exuParams.name}: WbPort must priority=0 or priority=1") 143 case _ => 144 } 145 } 146 val intWbPort = exuParams.getIntWBPort 147 if (intWbPort.isDefined){ 148 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 149 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 150 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 151 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 152 samePort.wbPortConfigs.map( 153 x => x match { 154 case IntWB(port, priority) => { 155 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 156 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 157 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 158 } 159 case _ => 160 } 161 ) 162 ) 163 } 164 val vfWbPort = exuParams.getVfWBPort 165 if (vfWbPort.isDefined) { 166 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 167 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 168 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 169 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 170 samePort.wbPortConfigs.map( 171 x => x match { 172 case VfWB(port, priority) => { 173 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 174 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 175 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 176 } 177 case _ => 178 } 179 ) 180 ) 181 } 182 if(backendParams.debugEn) { 183 dontTouch(io.out.ready) 184 } 185 // rob flush --> funcUnits 186 funcUnits.zipWithIndex.foreach { case (fu, i) => 187 fu.io.flush <> io.flush 188 } 189 190 def acceptCond(input: ExuInput): Seq[Bool] = { 191 input.params.fuConfigs.map(_.fuSel(input)) 192 } 193 194 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 195 196 // ExeUnit.in <---> Dispatcher.in 197 in1ToN.io.in.valid := io.in.valid && !busy 198 in1ToN.io.in.bits := io.in.bits 199 io.in.ready := !busy && in1ToN.io.in.ready 200 201 // Dispatcher.out <---> FunctionUnits 202 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 203 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 204 sink.valid := source.valid 205 source.ready := sink.ready 206 207 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 208 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 209 sink.bits.data.imm := source.bits.imm 210 sink.bits.ctrl.fuOpType := source.bits.fuOpType 211 sink.bits.ctrl.robIdx := source.bits.robIdx 212 sink.bits.ctrl.pdest := source.bits.pdest 213 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 214 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 215 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 216 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 217 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 218 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 219 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 220 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 221 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 222 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 223 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 224 } 225 226 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 227 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 228 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 229 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.res.redirect) 230 231 // Assume that one fu can only write int or fp or vec, 232 // otherwise, wenVec should be assigned to wen in fu. 233 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 234 private val fuFpWenVec = funcUnits.map(x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 235 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 236 // FunctionUnits <---> ExeUnit.out 237 io.out.valid := Cat(fuOutValidOH).orR 238 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 239 240 // select one fu's result 241 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.data)) 242 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 243 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 244 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 245 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 246 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 247 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 248 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 249 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 250 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 251 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 252 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 253 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 254 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 255 256 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 257 fuio => 258 exuio <> fuio 259 fuio.exception := DelayN(exuio.exception, 2) 260 })) 261 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 262 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 263 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 264 265 // debug info 266 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 267 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 268 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 269} 270 271class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 272 val in = Flipped(DecoupledIO(gen)) 273 274 val out = Vec(n, DecoupledIO(gen)) 275} 276 277class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 278 (implicit p: Parameters) 279 extends Module { 280 281 val io = IO(new DispatcherIO(gen, n)) 282 283 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 284 285 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 286 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 287 288 io.out.zipWithIndex.foreach { case (out, i) => 289 out.valid := acceptVec(i) && io.in.valid 290 out.bits := io.in.bits 291 } 292 293 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 294} 295 296class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 297 val flush = Flipped(ValidIO(new Redirect())) 298 val in = Flipped(DecoupledIO(new MemExuInput())) 299 val out = DecoupledIO(new MemExuOutput()) 300} 301 302class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 303 val io = IO(new MemExeUnitIO) 304 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 305 fu.io.flush := io.flush 306 fu.io.in.valid := io.in.valid 307 io.in.ready := fu.io.in.ready 308 309 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 310 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 311 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 312 fu.io.in.bits.data.imm := io.in.bits.uop.imm 313 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 314 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 315 316 io.out.valid := fu.io.out.valid 317 fu.io.out.ready := io.out.ready 318 319 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 320 io.out.bits.data := fu.io.out.bits.res.data 321 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 322 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 323 io.out.bits.uop.fuType := io.in.bits.uop.fuType 324 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 325 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 326 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 327 328 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 329} 330