1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.DelayN 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30 31class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 32 val flush = Flipped(ValidIO(new Redirect())) 33 val in = Flipped(DecoupledIO(new ExuInput(params))) 34 val out = DecoupledIO(new ExuOutput(params)) 35 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 36 val fenceio = if (params.hasFence) Some(new FenceIO) else None 37 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 38} 39 40class ExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 41 override def shouldBeInlined: Boolean = false 42 43 lazy val module = new ExeUnitImp(this)(p, exuParams) 44} 45 46class ExeUnitImp( 47 override val wrapper: ExeUnit 48)(implicit 49 p: Parameters, exuParams: ExeUnitParams 50) extends LazyModuleImp(wrapper) with HasXSParameter{ 51 private val fuCfgs = exuParams.fuConfigs 52 53 val io = IO(new ExeUnitIO(exuParams)) 54 55 val funcUnits = fuCfgs.map(cfg => { 56 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 57 val module = cfg.fuGen(p, cfg) 58 module 59 }) 60 61 val busy = RegInit(false.B) 62 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 63 when (io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 64 busy := false.B 65 }.elsewhen(busy && robIdx.needFlush(io.flush)){ 66 busy := false.B 67 }.elsewhen(io.out.fire) { 68 busy := false.B 69 }.elsewhen(io.in.fire) { 70 busy := true.B 71 } 72 73 if (exuParams.latencyCertain){ 74 busy := false.B 75 } 76 77 exuParams.wbPortConfigs.map{ 78 x => x match { 79 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 80 s"${exuParams.name}: WbPort must priority=0 or priority=1") 81 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 82 s"${exuParams.name}: WbPort must priority=0 or priority=1") 83 case _ => 84 } 85 } 86 val intWbPort = exuParams.getIntWBPort 87 if (intWbPort.isDefined){ 88 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 89 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 90 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 91 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 92 samePort.wbPortConfigs.map( 93 x => x match { 94 case IntWB(port, priority) => { 95 if (!samePort.latencyCertain) assert(priority == 1, 96 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 97 else assert(priority == 0, 98 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 99 } 100 case _ => 101 } 102 ) 103 ) 104 } 105 val vfWbPort = exuParams.getVfWBPort 106 if (vfWbPort.isDefined) { 107 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 108 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 109 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 110 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 111 samePort.wbPortConfigs.map( 112 x => x match { 113 case VfWB(port, priority) => { 114 if (!samePort.latencyCertain) assert(priority == 1, 115 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 116 else assert(priority == 0, 117 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 118 } 119 case _ => 120 } 121 ) 122 ) 123 } 124 dontTouch(io.out.ready) 125 // rob flush --> funcUnits 126 funcUnits.zipWithIndex.foreach { case (fu, i) => 127 fu.io.flush <> io.flush 128 } 129 130 def acceptCond(input: ExuInput): Seq[Bool] = { 131 input.params.fuConfigs.map(_.fuSel(input)) 132 } 133 134 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 135 136 // ExeUnit.in <---> Dispatcher.in 137 in1ToN.io.in.valid := io.in.valid && !busy 138 in1ToN.io.in.bits := io.in.bits 139 io.in.ready := !busy && in1ToN.io.in.ready 140 141 // Dispatcher.out <---> FunctionUnits 142 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 143 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 144 sink.valid := source.valid 145 source.ready := sink.ready 146 147 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 148 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 149 sink.bits.data.imm := source.bits.imm 150 sink.bits.ctrl.fuOpType := source.bits.fuOpType 151 sink.bits.ctrl.robIdx := source.bits.robIdx 152 sink.bits.ctrl.pdest := source.bits.pdest 153 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 154 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 155 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 156 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 157 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 158 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 159 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 160 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 161 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 162 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 163 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 164 } 165 166 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 167 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 168 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 169 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.res.redirect) 170 171 // Assume that one fu can only write int or fp or vec, 172 // otherwise, wenVec should be assigned to wen in fu. 173 private val fuIntWenVec = funcUnits.map(x => x.cfg.writeIntRf.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 174 private val fuFpWenVec = funcUnits.map(x => x.cfg.writeFpRf.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 175 private val fuVecWenVec = funcUnits.map(x => x.cfg.writeVecRf.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 176 // FunctionUnits <---> ExeUnit.out 177 io.out.valid := Cat(fuOutValidOH).orR 178 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 179 180 // select one fu's result 181 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.data)) 182 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 183 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 184 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 185 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 186 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 187 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 188 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 189 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 190 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 191 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 192 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 193 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 194 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 195 196 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 197 fuio => 198 exuio <> fuio 199 fuio.exception := DelayN(exuio.exception, 2) 200 })) 201 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 202 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 203 204 // debug info 205 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 206 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 207 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 208} 209 210class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 211 val in = Flipped(DecoupledIO(gen)) 212 213 val out = Vec(n, DecoupledIO(gen)) 214} 215 216class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 217 (implicit p: Parameters) 218 extends Module { 219 220 val io = IO(new DispatcherIO(gen, n)) 221 222 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 223 224 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 225 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 226 227 io.out.zipWithIndex.foreach { case (out, i) => 228 out.valid := acceptVec(i) && io.in.valid 229 out.bits := io.in.bits 230 } 231 232 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 233} 234 235class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 236 val flush = Flipped(ValidIO(new Redirect())) 237 val in = Flipped(DecoupledIO(new MemExuInput())) 238 val out = DecoupledIO(new MemExuOutput()) 239} 240 241class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 242 val io = IO(new MemExeUnitIO) 243 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 244 fu.io.flush := io.flush 245 fu.io.in.valid := io.in.valid 246 io.in.ready := fu.io.in.ready 247 248 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 249 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 250 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 251 fu.io.in.bits.data.imm := io.in.bits.uop.imm 252 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 253 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 254 255 io.out.valid := fu.io.out.valid 256 fu.io.out.ready := io.out.ready 257 258 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 259 io.out.bits.data := fu.io.out.bits.res.data 260 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 261 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 262 io.out.bits.uop.fuType := io.in.bits.uop.fuType 263 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 264 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 265 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 266 267 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 268} 269