1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.DelayN 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30 31class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 32 val flush = Flipped(ValidIO(new Redirect())) 33 val in = Flipped(DecoupledIO(new ExuInput(params))) 34 val out = DecoupledIO(new ExuOutput(params)) 35 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 36 val fenceio = if (params.hasFence) Some(new FenceIO) else None 37 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 38} 39 40class ExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 41 lazy val module = new ExeUnitImp(this)(p, exuParams) 42} 43 44class ExeUnitImp( 45 override val wrapper: ExeUnit 46)(implicit 47 p: Parameters, exuParams: ExeUnitParams 48) extends LazyModuleImp(wrapper) with HasXSParameter{ 49 private val fuCfgs = exuParams.fuConfigs 50 51 val io = IO(new ExeUnitIO(exuParams)) 52 53 val funcUnits = fuCfgs.map(cfg => { 54 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 55 val module = cfg.fuGen(p, cfg) 56 module 57 }) 58 59 val busy = RegInit(false.B) 60 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 61 when (io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 62 busy := false.B 63 }.elsewhen(busy && robIdx.needFlush(io.flush)){ 64 busy := false.B 65 }.elsewhen(io.out.fire) { 66 busy := false.B 67 }.elsewhen(io.in.fire) { 68 busy := true.B 69 } 70 71 if (exuParams.latencyCertain){ 72 busy := false.B 73 } 74 75 exuParams.wbPortConfigs.map{ 76 x => x match { 77 case IntWB(port, priority) => assert((priority == 0) || (priority == 1), 78 s"${exuParams.name}: WbPort must priority=0 or priority=1") 79 case VfWB (port, priority) => assert((priority == 0) || (priority == 1), 80 s"${exuParams.name}: WbPort must priority=0 or priority=1") 81 case _ => 82 } 83 } 84 val intWbPort = exuParams.getIntWBPort 85 if (intWbPort.isDefined){ 86 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 87 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 88 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 89 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 90 samePort.wbPortConfigs.map( 91 x => x match { 92 case IntWB(port, priority) => { 93 if (!samePort.latencyCertain) assert(priority == 1, 94 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 95 else assert(priority == 0, 96 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 97 } 98 case _ => 99 } 100 ) 101 ) 102 } 103 val vfWbPort = exuParams.getVfWBPort 104 if (vfWbPort.isDefined) { 105 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 106 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 107 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 108 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 109 samePort.wbPortConfigs.map( 110 x => x match { 111 case VfWB(port, priority) => { 112 if (!samePort.latencyCertain) assert(priority == 1, 113 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 114 else assert(priority == 0, 115 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 116 } 117 case _ => 118 } 119 ) 120 ) 121 } 122 dontTouch(io.out.ready) 123 // rob flush --> funcUnits 124 funcUnits.zipWithIndex.foreach { case (fu, i) => 125 fu.io.flush <> io.flush 126 } 127 128 def acceptCond(input: ExuInput): Seq[Bool] = { 129 input.params.fuConfigs.map(_.fuSel(input)) 130 } 131 132 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 133 134 // ExeUnit.in <---> Dispatcher.in 135 in1ToN.io.in.valid := io.in.valid && !busy 136 in1ToN.io.in.bits := io.in.bits 137 io.in.ready := !busy && in1ToN.io.in.ready 138 139 // Dispatcher.out <---> FunctionUnits 140 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 141 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 142 sink.valid := source.valid 143 source.ready := sink.ready 144 145 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 146 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 147 sink.bits.data.imm := source.bits.imm 148 sink.bits.ctrl.fuOpType := source.bits.fuOpType 149 sink.bits.ctrl.robIdx := source.bits.robIdx 150 sink.bits.ctrl.pdest := source.bits.pdest 151 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 152 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 153 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 154 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 155 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 156 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 157 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 158 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 159 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 160 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 161 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 162 } 163 164 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 165 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 166 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 167 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.res.redirect) 168 169 // Assume that one fu can only write int or fp or vec, 170 // otherwise, wenVec should be assigned to wen in fu. 171 private val fuIntWenVec = funcUnits.map(x => x.cfg.writeIntRf.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 172 private val fuFpWenVec = funcUnits.map(x => x.cfg.writeFpRf.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 173 private val fuVecWenVec = funcUnits.map(x => x.cfg.writeVecRf.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 174 // FunctionUnits <---> ExeUnit.out 175 io.out.valid := Cat(fuOutValidOH).orR 176 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 177 178 // select one fu's result 179 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.data)) 180 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 181 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 182 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 183 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 184 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 185 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 186 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 187 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 188 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 189 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 190 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 191 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 192 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 193 194 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 195 fuio => 196 exuio <> fuio 197 fuio.exception := DelayN(exuio.exception, 2) 198 })) 199 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 200 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 201 202 // debug info 203 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 204 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 205 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 206} 207 208class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 209 val in = Flipped(DecoupledIO(gen)) 210 211 val out = Vec(n, DecoupledIO(gen)) 212} 213 214class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 215 (implicit p: Parameters) 216 extends Module { 217 218 val io = IO(new DispatcherIO(gen, n)) 219 220 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 221 222 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 223 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 224 225 io.out.zipWithIndex.foreach { case (out, i) => 226 out.valid := acceptVec(i) && io.in.valid 227 out.bits := io.in.bits 228 } 229 230 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 231} 232 233class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 234 val flush = Flipped(ValidIO(new Redirect())) 235 val in = Flipped(DecoupledIO(new MemExuInput())) 236 val out = DecoupledIO(new MemExuOutput()) 237} 238 239class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 240 val io = IO(new MemExeUnitIO) 241 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 242 fu.io.flush := io.flush 243 fu.io.in.valid := io.in.valid 244 io.in.ready := fu.io.in.ready 245 246 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 247 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 248 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 249 fu.io.in.bits.data.imm := io.in.bits.uop.imm 250 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 251 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 252 253 io.out.valid := fu.io.out.valid 254 fu.io.out.ready := io.out.ready 255 256 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 257 io.out.bits.data := fu.io.out.bits.res.data 258 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 259 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 260 io.out.bits.uop.fuType := io.in.bits.uop.fuType 261 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 262 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 263 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 264 265 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 266} 267