1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.experimental.hierarchy.{Definition, instantiable, public} 23import chisel3.util._ 24import utils._ 25import xiangshan._ 26import xiangshan.backend.fu.fpu.{FMA, FPUSubModule} 27import xiangshan.backend.fu.{CSR, FUWithRedirect, Fence, FenceToSbuffer} 28 29class FenceIO(implicit p: Parameters) extends XSBundle { 30 val sfence = Output(new SfenceBundle) 31 val fencei = Output(Bool()) 32 val sbuffer = new FenceToSbuffer 33} 34 35@instantiable 36class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) { 37 38 val disableSfence = WireInit(false.B) 39 val csr_frm = WireInit(frm.getOrElse(0.U(3.W))) 40 41 val hasRedirect = config.fuConfigs.zip(functionUnits).filter(_._1.hasRedirect).map(_._2) 42 println(s"${functionUnits} ${hasRedirect} hasRedirect: ${hasRedirect.length}") 43 if (hasRedirect.nonEmpty) { 44 require(hasRedirect.length <= 1) 45 io.out.bits.redirectValid := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOutValid 46 io.out.bits.redirect := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOut 47 } 48 49 if (config.fuConfigs.contains(csrCfg)) { 50 val csr = functionUnits.collectFirst{ 51 case c: CSR => c 52 }.get 53 csr.csrio <> csrio.get 54 csrio.get.tlb := DelayN(csr.csrio.tlb, 2) 55 csrio.get.customCtrl := DelayN(csr.csrio.customCtrl, 2) 56 csrio.get.trapTarget := RegNext(csr.csrio.trapTarget) 57 csr.csrio.exception := DelayN(csrio.get.exception, 2) 58 disableSfence := csr.csrio.disableSfence 59 csr_frm := csr.csrio.fpu.frm 60 // setup skip for hpm CSR read 61 io.out.bits.debug.isPerfCnt := RegNext(csr.csrio.isPerfCnt) // TODO: this is dirty 62 } 63 64 if (config.fuConfigs.contains(fenceCfg)) { 65 val fence = functionUnits.collectFirst{ 66 case f: Fence => f 67 }.get 68 fenceio.get.sfence <> fence.sfence 69 fenceio.get.fencei <> fence.fencei 70 fenceio.get.sbuffer <> fence.toSbuffer 71 fence.io.out.ready := true.B 72 fence.disableSfence := disableSfence 73 } 74 75 val fpModules = functionUnits.zip(config.fuConfigs.zipWithIndex).filter(_._1.isInstanceOf[FPUSubModule]) 76 if (fpModules.nonEmpty) { 77 // frm is from csr/frm (from CSR) or instr_rm (from instruction decoding) 78 val fpSubModules = fpModules.map(_._1.asInstanceOf[FPUSubModule]) 79 fpSubModules.foreach(mod => { 80 val instr_rm = mod.io.in.bits.uop.ctrl.fpu.rm 81 mod.rm := Mux(instr_rm =/= 7.U, instr_rm, csr_frm) 82 }) 83 // fflags is selected by arbSelReg 84 require(config.hasFastUopOut, "non-fast not implemented") 85 val fflagsSel = fpModules.map{ case (fu, (cfg, i)) => 86 val fflagsValid = arbSelReg(i) 87 val fflags = fu.asInstanceOf[FPUSubModule].fflags 88 val fflagsBits = if (cfg.fastImplemented) fflags else RegNext(fflags) 89 (fflagsValid, fflagsBits) 90 } 91 io.out.bits.fflags := Mux1H(fflagsSel.map(_._1), fflagsSel.map(_._2)) 92 } 93 94 val fmaModules = functionUnits.filter(_.isInstanceOf[FMA]).map(_.asInstanceOf[FMA]) 95 if (fmaModules.nonEmpty) { 96 require(fmaModules.length == 1) 97 fmaModules.head.midResult <> fmaMid.get 98 } 99 100 if (config.readIntRf) { 101 val in = io.fromInt 102 val out = io.out 103 XSDebug(in.valid, p"fromInt(${in.valid} ${in.ready}) toInt(${out.valid} ${out.ready})\n") 104 XSDebug(io.redirect.valid, p"Redirect:(${io.redirect.valid}) robIdx:${io.redirect.bits.robIdx}\n") 105 XSDebug(in.valid, p"src1:${Hexadecimal(in.bits.src(0))} src2:${Hexadecimal(in.bits.src(1))} " + 106 p"func:${Binary(in.bits.uop.ctrl.fuOpType)} pc:${Hexadecimal(in.bits.uop.cf.pc)} robIdx:${in.bits.uop.robIdx}\n") 107 XSDebug(out.valid, p"out res:${Hexadecimal(out.bits.data)} robIdx:${out.bits.uop.robIdx}\n") 108 } 109 110} 111 112class AluExeUnit(implicit p: Parameters) extends ExeUnit(AluExeUnitCfg) 113class JumpCSRExeUnit(implicit p: Parameters) extends ExeUnit(JumpCSRExeUnitCfg) 114class JumpExeUnit(implicit p: Parameters) extends ExeUnit(JumpExeUnitCfg) 115class StdExeUnit(implicit p: Parameters) extends ExeUnit(StdExeUnitCfg) 116class FmacExeUnit(implicit p: Parameters) extends ExeUnit(FmacExeUnitCfg) 117class FmiscExeUnit(implicit p: Parameters) extends ExeUnit(FmiscExeUnitCfg) 118 119object ExeUnitDef { 120 def apply(cfg: ExuConfig)(implicit p: Parameters): Definition[ExeUnit] = { 121 cfg match { 122 case JumpExeUnitCfg => Definition(new JumpExeUnit) 123 case AluExeUnitCfg => Definition(new AluExeUnit) 124 case MulDivExeUnitCfg => Definition(new MulDivExeUnit) 125 case JumpCSRExeUnitCfg => Definition(new JumpCSRExeUnit) 126 case FmacExeUnitCfg => Definition(new FmacExeUnit) 127 case FmiscExeUnitCfg => Definition(new FmiscExeUnit) 128 case StdExeUnitCfg => Definition(new StdExeUnit) 129 case _ => { 130 println(s"cannot generate exeUnit from $cfg") 131 null 132 } 133 } 134 } 135} 136 137