1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility._ 25import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 26import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 27import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 28import xiangshan.backend.datapath.WbConfig.{PregWB, _} 29import xiangshan.backend.fu.FuType 30import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm} 31import xiangshan.backend.fu.fpu.Bundles.Frm 32import xiangshan.backend.fu.wrapper.CSRInput 33 34class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 35 val flush = Flipped(ValidIO(new Redirect())) 36 val in = Flipped(DecoupledIO(new ExuInput(params))) 37 val out = DecoupledIO(new ExuOutput(params)) 38 val csrin = Option.when(params.hasCSR)(new CSRInput) 39 val csrio = Option.when(params.hasCSR)(new CSRFileIO) 40 val fenceio = Option.when(params.hasFence)(new FenceIO) 41 val frm = Option.when(params.needSrcFrm)(Input(Frm())) 42 val vxrm = Option.when(params.needSrcVxrm)(Input(Vxrm())) 43 val vtype = Option.when(params.writeVConfig)((Valid(new VType))) 44 val vlIsZero = Option.when(params.writeVConfig)(Output(Bool())) 45 val vlIsVlmax = Option.when(params.writeVConfig)(Output(Bool())) 46} 47 48class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 49 override def shouldBeInlined: Boolean = false 50 51 lazy val module = new ExeUnitImp(this)(p, exuParams) 52} 53 54class ExeUnitImp( 55 override val wrapper: ExeUnit 56)(implicit 57 p: Parameters, exuParams: ExeUnitParams 58) extends LazyModuleImp(wrapper) with HasXSParameter{ 59 private val fuCfgs = exuParams.fuConfigs 60 61 val io = IO(new ExeUnitIO(exuParams)) 62 63 val funcUnits = fuCfgs.map(cfg => { 64 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 65 val module = cfg.fuGen(p, cfg) 66 module 67 }) 68 69 if (EnableClockGate) { 70 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 71 val clk_en = WireInit(false.B) 72 val fuVld_en = WireInit(false.B) 73 val fuVld_en_reg = RegInit(false.B) 74 val uncer_en_reg = RegInit(false.B) 75 76 def latReal: Int = cfg.latency.latencyVal.getOrElse(0) 77 def extralat: Int = cfg.latency.extraLatencyVal.getOrElse(0) 78 79 val uncerLat = cfg.latency.uncertainEnable.nonEmpty 80 val lat0 = (latReal == 0 && !uncerLat).asBool 81 val latN = (latReal > 0 && !uncerLat).asBool 82 83 val fuVldVec = (io.in.valid && latN) +: Seq.fill(latReal)(RegInit(false.B)) 84 val fuRdyVec = Seq.fill(latReal)(Wire(Bool())) :+ io.out.ready 85 86 for (i <- 0 until latReal) { 87 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 88 } 89 90 for (i <- 1 to latReal) { 91 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 92 fuVldVec(i) := fuVldVec(i - 1) 93 }.elsewhen(fuRdyVec(i)) { 94 fuVldVec(i) := false.B 95 } 96 } 97 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 98 fuVld_en_reg := fuVld_en 99 100 when(uncerLat.asBool && io.in.fire) { 101 uncer_en_reg := true.B 102 }.elsewhen(uncerLat.asBool && io.out.fire) { 103 uncer_en_reg := false.B 104 } 105 106 when(lat0 && io.in.fire) { 107 clk_en := true.B 108 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 109 clk_en := true.B 110 }.elsewhen(uncerLat.asBool && io.in.fire || uncer_en_reg) { 111 clk_en := true.B 112 } 113 114 if (cfg.ckAlwaysEn) { 115 clk_en := true.B 116 } 117 118 fu.clock := ClockGate(false.B, clk_en, clock) 119 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 120 } 121 } 122 123 val busy = RegInit(false.B) 124 if (exuParams.latencyCertain){ 125 busy := false.B 126 } 127 else { 128 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 129 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 130 busy := false.B 131 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 132 busy := false.B 133 }.elsewhen(io.out.fire) { 134 busy := false.B 135 }.elsewhen(io.in.fire) { 136 busy := true.B 137 } 138 } 139 140 exuParams.wbPortConfigs.map{ 141 x => x match { 142 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 143 s"${exuParams.name}: WbPort must priority=0 or priority=1") 144 case FpWB(port, priority) => assert(priority >= 0 && priority <= 2, 145 s"${exuParams.name}: WbPort must priority=0 or priority=1") 146 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 147 s"${exuParams.name}: WbPort must priority=0 or priority=1") 148 case _ => 149 } 150 } 151 val intWbPort = exuParams.getIntWBPort 152 if (intWbPort.isDefined){ 153 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 154 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 155 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 156 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 157 samePort.wbPortConfigs.map( 158 x => x match { 159 case IntWB(port, priority) => { 160 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 161 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 162 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 163 } 164 case _ => 165 } 166 ) 167 ) 168 } 169 val fpWbPort = exuParams.getFpWBPort 170 if (fpWbPort.isDefined) { 171 val sameFpPortExuParam = backendParams.allExuParams.filter(_.getFpWBPort.isDefined) 172 .filter(_.getFpWBPort.get.port == fpWbPort.get.port) 173 val samePortOneCertainOneUncertain = sameFpPortExuParam.map(_.latencyCertain).contains(true) && sameFpPortExuParam.map(_.latencyCertain).contains(false) 174 if (samePortOneCertainOneUncertain) sameFpPortExuParam.map(samePort => 175 samePort.wbPortConfigs.map( 176 x => x match { 177 case FpWB(port, priority) => { 178 if (!samePort.latencyCertain) assert(priority == sameFpPortExuParam.size - 1, 179 s"${samePort.name}: FpWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameFpPortExuParam.size - 1})") 180 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 181 } 182 case _ => 183 } 184 ) 185 ) 186 } 187 val vfWbPort = exuParams.getVfWBPort 188 if (vfWbPort.isDefined) { 189 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 190 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 191 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 192 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 193 samePort.wbPortConfigs.map( 194 x => x match { 195 case VfWB(port, priority) => { 196 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 197 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 198 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 199 } 200 case _ => 201 } 202 ) 203 ) 204 } 205 if(backendParams.debugEn) { 206 dontTouch(io.out.ready) 207 } 208 // rob flush --> funcUnits 209 funcUnits.zipWithIndex.foreach { case (fu, i) => 210 fu.io.flush <> io.flush 211 } 212 213 def acceptCond(input: ExuInput): Seq[Bool] = { 214 input.params.fuConfigs.map(_.fuSel(input)) 215 } 216 217 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 218 219 // ExeUnit.in <---> Dispatcher.in 220 in1ToN.io.in.valid := io.in.valid && !busy 221 in1ToN.io.in.bits := io.in.bits 222 io.in.ready := !busy && in1ToN.io.in.ready 223 224 // Dispatcher.out <---> FunctionUnits 225 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 226 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 227 sink.valid := source.valid 228 source.ready := sink.ready 229 230 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 231 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 232 sink.bits.data.imm := source.bits.imm 233 sink.bits.ctrl.fuOpType := source.bits.fuOpType 234 sink.bits.ctrl.robIdx := source.bits.robIdx 235 sink.bits.ctrl.pdest := source.bits.pdest 236 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 237 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 238 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 239 sink.bits.ctrl.v0Wen .foreach(x => x := source.bits.v0Wen.get) 240 sink.bits.ctrl.vlWen .foreach(x => x := source.bits.vlWen.get) 241 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 242 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 243 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 244 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 245 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 246 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 247 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 248 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFpToVecInst := 0.U) 249 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP32Instr := 0.U) 250 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP64Instr := 0.U) 251 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 252 } 253 254 private val OutresVecs = funcUnits.map { fu => 255 def latDiff :Int = fu.cfg.latency.extraLatencyVal.getOrElse(0) 256 val OutresVec = fu.io.out.bits.res +: Seq.fill(latDiff)(Reg(chiselTypeOf(fu.io.out.bits.res))) 257 for (i <- 1 to latDiff) { 258 OutresVec(i) := OutresVec(i - 1) 259 } 260 OutresVec 261 } 262 OutresVecs.foreach(vec => vec.foreach(res =>dontTouch(res))) 263 264 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 265 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 266 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 267 private val fuOutresVec = OutresVecs.map(_.last) 268 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = fuOutresVec.map(_.redirect) 269 270 // Assume that one fu can only write int or fp or vec, 271 // otherwise, wenVec should be assigned to wen in fu. 272 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 273 private val fuFpWenVec = funcUnits.map(x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 274 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 275 private val fuV0WenVec = funcUnits.map(x => x.cfg.needV0Wen.B && x.io.out.bits.ctrl.v0Wen.getOrElse(false.B)) 276 private val fuVlWenVec = funcUnits.map(x => x.cfg.needVlWen.B && x.io.out.bits.ctrl.vlWen.getOrElse(false.B)) 277 // FunctionUnits <---> ExeUnit.out 278 279 private val outDataVec = Seq( 280 Some(fuOutresVec.map(_.data)), 281 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 282 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuout) => fuout.data}), 283 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 284 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuout) => fuout.data}), 285 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 286 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuout) => fuout.data}), 287 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 288 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuout) => fuout.data}), 289 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 290 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuout) => fuout.data}), 291 ).flatten 292 private val outDataValidOH = Seq( 293 Some(fuOutValidOH), 294 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 295 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuoutOH) => fuoutOH}), 296 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 297 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuoutOH) => fuoutOH}), 298 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 299 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuoutOH) => fuoutOH}), 300 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 301 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuoutOH) => fuoutOH}), 302 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 303 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuoutOH) => fuoutOH}), 304 ).flatten 305 306 io.out.valid := Cat(fuOutValidOH).orR 307 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 308 309 // select one fu's result 310 io.out.bits.data := VecInit(outDataVec.zip(outDataValidOH).map{ case(data, validOH) => Mux1H(validOH, data)}) 311 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 312 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 313 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 314 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 315 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 316 io.out.bits.v0Wen.foreach(x => x := Mux1H(fuOutValidOH, fuV0WenVec)) 317 io.out.bits.vlWen.foreach(x => x := Mux1H(fuOutValidOH, fuVlWenVec)) 318 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 319 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 320 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 321 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 322 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 323 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 324 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 325 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 326 327 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 328 fuio => 329 exuio <> fuio 330 fuio.exception := DelayN(exuio.exception, 2) 331 })) 332 io.csrin.foreach(exuio => funcUnits.foreach(fu => fu.io.csrin.foreach{fuio => fuio := exuio})) 333 334 io.vtype.foreach(exuio => funcUnits.foreach(fu => fu.io.vtype.foreach(fuio => exuio := fuio))) 335 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 336 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 337 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 338 io.vlIsZero.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsZero.foreach(fuio => exuio := fuio))) 339 io.vlIsVlmax.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsVlmax.foreach(fuio => exuio := fuio))) 340 341 // debug info 342 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 343 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 344 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 345} 346 347class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 348 val in = Flipped(DecoupledIO(gen)) 349 350 val out = Vec(n, DecoupledIO(gen)) 351} 352 353class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 354 (implicit p: Parameters) 355 extends Module { 356 357 val io = IO(new DispatcherIO(gen, n)) 358 359 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 360 361 XSError(io.in.valid && PopCount(acceptVec) > 1.U, p"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 362 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 363 364 io.out.zipWithIndex.foreach { case (out, i) => 365 out.valid := acceptVec(i) && io.in.valid 366 out.bits := io.in.bits 367 } 368 369 io.in.ready := Cat(io.out.map(_.ready)).andR 370} 371 372class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 373 val flush = Flipped(ValidIO(new Redirect())) 374 val in = Flipped(DecoupledIO(new MemExuInput())) 375 val out = DecoupledIO(new MemExuOutput()) 376} 377 378class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 379 val io = IO(new MemExeUnitIO) 380 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 381 fu.io.flush := io.flush 382 fu.io.in.valid := io.in.valid 383 io.in.ready := fu.io.in.ready 384 385 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 386 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 387 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 388 fu.io.in.bits.data.imm := io.in.bits.uop.imm 389 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 390 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 391 392 io.out.valid := fu.io.out.valid 393 fu.io.out.ready := io.out.ready 394 395 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 396 io.out.bits.data := fu.io.out.bits.res.data 397 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 398 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 399 io.out.bits.uop.fuType := io.in.bits.uop.fuType 400 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 401 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 402 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 403 404 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 405}