1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility._ 25import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 26import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 27import xiangshan.{AddrTransType, FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 28import xiangshan.backend.datapath.WbConfig.{PregWB, _} 29import xiangshan.backend.fu.FuType 30import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm} 31import xiangshan.backend.fu.fpu.Bundles.Frm 32import xiangshan.backend.fu.wrapper.{CSRInput, CSRToDecode} 33 34class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 35 val flush = Flipped(ValidIO(new Redirect())) 36 val in = Flipped(DecoupledIO(new ExuInput(params))) 37 val out = DecoupledIO(new ExuOutput(params)) 38 val csrin = Option.when(params.hasCSR)(new CSRInput) 39 val csrio = Option.when(params.hasCSR)(new CSRFileIO) 40 val csrToDecode = Option.when(params.hasCSR)(Output(new CSRToDecode)) 41 val fenceio = Option.when(params.hasFence)(new FenceIO) 42 val frm = Option.when(params.needSrcFrm)(Input(Frm())) 43 val vxrm = Option.when(params.needSrcVxrm)(Input(Vxrm())) 44 val vtype = Option.when(params.writeVConfig)((Valid(new VType))) 45 val vlIsZero = Option.when(params.writeVConfig)(Output(Bool())) 46 val vlIsVlmax = Option.when(params.writeVConfig)(Output(Bool())) 47 val instrAddrTransType = Option.when(params.hasJmpFu || params.hasBrhFu)(Input(new AddrTransType)) 48} 49 50class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 51 override def shouldBeInlined: Boolean = false 52 53 lazy val module = new ExeUnitImp(this)(p, exuParams) 54} 55 56class ExeUnitImp( 57 override val wrapper: ExeUnit 58)(implicit 59 p: Parameters, exuParams: ExeUnitParams 60) extends LazyModuleImp(wrapper) with HasXSParameter with HasCriticalErrors { 61 private val fuCfgs = exuParams.fuConfigs 62 63 val io = IO(new ExeUnitIO(exuParams)) 64 65 val funcUnits = fuCfgs.map(cfg => { 66 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 67 val module = cfg.fuGen(p, cfg) 68 module 69 }) 70 71 if (EnableClockGate) { 72 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 73 val clk_en = WireInit(false.B) 74 val fuVld_en = WireInit(false.B) 75 val fuVld_en_reg = RegInit(false.B) 76 val uncer_en_reg = RegInit(false.B) 77 78 def latReal: Int = cfg.latency.latencyVal.getOrElse(0) 79 def extralat: Int = cfg.latency.extraLatencyVal.getOrElse(0) 80 81 val uncerLat = cfg.latency.uncertainEnable.nonEmpty 82 val lat0 = (latReal == 0 && !uncerLat).asBool 83 val latN = (latReal > 0 && !uncerLat).asBool 84 85 val fuVldVec = (fu.io.in.valid && latN) +: Seq.fill(latReal)(RegInit(false.B)) 86 val fuRdyVec = Seq.fill(latReal)(Wire(Bool())) :+ fu.io.out.ready 87 88 for (i <- 0 until latReal) { 89 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 90 } 91 92 for (i <- 1 to latReal) { 93 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 94 fuVldVec(i) := fuVldVec(i - 1) 95 }.elsewhen(fuRdyVec(i)) { 96 fuVldVec(i) := false.B 97 } 98 } 99 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 100 fuVld_en_reg := fuVld_en 101 102 when(uncerLat.asBool && fu.io.in.fire) { 103 uncer_en_reg := true.B 104 }.elsewhen(uncerLat.asBool && fu.io.out.fire) { 105 uncer_en_reg := false.B 106 } 107 108 when(lat0 && fu.io.in.fire) { 109 clk_en := true.B 110 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 111 clk_en := true.B 112 }.elsewhen(uncerLat.asBool && fu.io.in.fire || uncer_en_reg) { 113 clk_en := true.B 114 } 115 116 if (cfg.ckAlwaysEn) { 117 clk_en := true.B 118 } 119 120 if (latReal != 0 || uncerLat) { 121 fu.clock := ClockGate(false.B, clk_en, clock) 122 } 123 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 124 } 125 } 126 127 val busy = RegInit(false.B) 128 if (exuParams.latencyCertain){ 129 busy := false.B 130 } 131 else { 132 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 133 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 134 busy := false.B 135 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 136 busy := false.B 137 }.elsewhen(io.out.fire) { 138 busy := false.B 139 }.elsewhen(io.in.fire) { 140 busy := true.B 141 } 142 } 143 144 exuParams.wbPortConfigs.map{ 145 x => x match { 146 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 147 s"${exuParams.name}: WbPort must priority=0 or priority=1") 148 case FpWB(port, priority) => assert(priority >= 0 && priority <= 2, 149 s"${exuParams.name}: WbPort must priority=0 or priority=1") 150 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 151 s"${exuParams.name}: WbPort must priority=0 or priority=1") 152 case _ => 153 } 154 } 155 val intWbPort = exuParams.getIntWBPort 156 if (intWbPort.isDefined){ 157 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 158 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 159 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 160 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 161 samePort.wbPortConfigs.map( 162 x => x match { 163 case IntWB(port, priority) => { 164 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 165 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 166 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 167 } 168 case _ => 169 } 170 ) 171 ) 172 } 173 val fpWbPort = exuParams.getFpWBPort 174 if (fpWbPort.isDefined) { 175 val sameFpPortExuParam = backendParams.allExuParams.filter(_.getFpWBPort.isDefined) 176 .filter(_.getFpWBPort.get.port == fpWbPort.get.port) 177 val samePortOneCertainOneUncertain = sameFpPortExuParam.map(_.latencyCertain).contains(true) && sameFpPortExuParam.map(_.latencyCertain).contains(false) 178 if (samePortOneCertainOneUncertain) sameFpPortExuParam.map(samePort => 179 samePort.wbPortConfigs.map( 180 x => x match { 181 case FpWB(port, priority) => { 182 if (!samePort.latencyCertain) assert(priority == sameFpPortExuParam.size - 1, 183 s"${samePort.name}: FpWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameFpPortExuParam.size - 1})") 184 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 185 } 186 case _ => 187 } 188 ) 189 ) 190 } 191 val vfWbPort = exuParams.getVfWBPort 192 if (vfWbPort.isDefined) { 193 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 194 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 195 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 196 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 197 samePort.wbPortConfigs.map( 198 x => x match { 199 case VfWB(port, priority) => { 200 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 201 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 202 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 203 } 204 case _ => 205 } 206 ) 207 ) 208 } 209 if(backendParams.debugEn) { 210 dontTouch(io.out.ready) 211 } 212 // rob flush --> funcUnits 213 funcUnits.zipWithIndex.foreach { case (fu, i) => 214 fu.io.flush <> io.flush 215 } 216 217 def acceptCond(input: ExuInput): Seq[Bool] = { 218 input.params.fuConfigs.map(_.fuSel(input)) 219 } 220 221 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 222 223 // ExeUnit.in <---> Dispatcher.in 224 in1ToN.io.in.valid := io.in.valid && !busy 225 in1ToN.io.in.bits := io.in.bits 226 io.in.ready := !busy && in1ToN.io.in.ready 227 228 // Dispatcher.out <---> FunctionUnits 229 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 230 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 231 sink.valid := source.valid 232 source.ready := sink.ready 233 234 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 235 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 236 sink.bits.data.imm := source.bits.imm 237 sink.bits.ctrl.fuOpType := source.bits.fuOpType 238 sink.bits.ctrl.robIdx := source.bits.robIdx 239 sink.bits.ctrl.pdest := source.bits.pdest 240 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 241 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 242 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 243 sink.bits.ctrl.v0Wen .foreach(x => x := source.bits.v0Wen.get) 244 sink.bits.ctrl.vlWen .foreach(x => x := source.bits.vlWen.get) 245 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 246 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 247 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 248 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 249 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 250 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 251 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 252 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFpToVecInst := 0.U) 253 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP32Instr := 0.U) 254 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP64Instr := 0.U) 255 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 256 } 257 258 private val OutresVecs = funcUnits.map { fu => 259 def latDiff :Int = fu.cfg.latency.extraLatencyVal.getOrElse(0) 260 val OutresVec = fu.io.out.bits.res +: Seq.fill(latDiff)(Reg(chiselTypeOf(fu.io.out.bits.res))) 261 for (i <- 1 to latDiff) { 262 OutresVec(i) := OutresVec(i - 1) 263 } 264 OutresVec 265 } 266 OutresVecs.foreach(vec => vec.foreach(res =>dontTouch(res))) 267 268 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 269 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 270 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 271 private val fuOutresVec = OutresVecs.map(_.last) 272 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = fuOutresVec.map(_.redirect) 273 274 // Assume that one fu can only write int or fp or vec, 275 // otherwise, wenVec should be assigned to wen in fu. 276 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 277 private val fuFpWenVec = funcUnits.map( x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 278 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 279 private val fuV0WenVec = funcUnits.map(x => x.cfg.needV0Wen.B && x.io.out.bits.ctrl.v0Wen.getOrElse(false.B)) 280 private val fuVlWenVec = funcUnits.map(x => x.cfg.needVlWen.B && x.io.out.bits.ctrl.vlWen.getOrElse(false.B)) 281 // FunctionUnits <---> ExeUnit.out 282 283 private val outDataVec = Seq( 284 Some(fuOutresVec.map(_.data)), 285 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 286 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuout) => fuout.data}), 287 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 288 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuout) => fuout.data}), 289 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 290 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuout) => fuout.data}), 291 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 292 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuout) => fuout.data}), 293 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 294 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuout) => fuout.data}), 295 ).flatten 296 private val outDataValidOH = Seq( 297 Some(fuOutValidOH), 298 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 299 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuoutOH) => fuoutOH}), 300 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 301 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuoutOH) => fuoutOH}), 302 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 303 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuoutOH) => fuoutOH}), 304 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 305 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuoutOH) => fuoutOH}), 306 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 307 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuoutOH) => fuoutOH}), 308 ).flatten 309 310 val criticalErrors = funcUnits.filter(fu => fu.cfg.needCriticalErrors).flatMap(fu => fu.getCriticalErrors) 311 generateCriticalErrors() 312 313 io.out.valid := Cat(fuOutValidOH).orR 314 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 315 316 // select one fu's result 317 io.out.bits.data := VecInit(outDataVec.zip(outDataValidOH).map{ case(data, validOH) => Mux1H(validOH, data)}) 318 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 319 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 320 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 321 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 322 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 323 io.out.bits.v0Wen.foreach(x => x := Mux1H(fuOutValidOH, fuV0WenVec)) 324 io.out.bits.vlWen.foreach(x => x := Mux1H(fuOutValidOH, fuVlWenVec)) 325 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 326 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 327 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 328 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 329 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 330 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 331 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 332 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 333 334 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 335 fuio => 336 exuio <> fuio 337 fuio.exception := DelayN(exuio.exception, 2) 338 fuio.robDeqPtr := DelayN(exuio.robDeqPtr, 2) 339 })) 340 io.csrin.foreach(exuio => funcUnits.foreach(fu => fu.io.csrin.foreach{fuio => fuio := exuio})) 341 io.csrToDecode.foreach(toDecode => funcUnits.foreach(fu => fu.io.csrToDecode.foreach(fuOut => toDecode := fuOut))) 342 343 io.vtype.foreach(exuio => funcUnits.foreach(fu => fu.io.vtype.foreach(fuio => exuio := fuio))) 344 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 345 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 346 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 347 io.vlIsZero.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsZero.foreach(fuio => exuio := fuio))) 348 io.vlIsVlmax.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsVlmax.foreach(fuio => exuio := fuio))) 349 io.instrAddrTransType.foreach(exuio => funcUnits.foreach(fu => fu.io.instrAddrTransType.foreach(fuio => fuio := exuio))) 350 351 // debug info 352 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 353 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 354 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 355} 356 357class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 358 val in = Flipped(DecoupledIO(gen)) 359 360 val out = Vec(n, DecoupledIO(gen)) 361} 362 363class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 364 (implicit p: Parameters) 365 extends Module { 366 367 val io = IO(new DispatcherIO(gen, n)) 368 369 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 370 371 XSError(io.in.valid && PopCount(acceptVec) > 1.U, p"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 372 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 373 374 io.out.zipWithIndex.foreach { case (out, i) => 375 out.valid := acceptVec(i) && io.in.valid 376 out.bits := io.in.bits 377 } 378 379 io.in.ready := Cat(io.out.map(_.ready)).andR 380} 381 382class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 383 val flush = Flipped(ValidIO(new Redirect())) 384 val in = Flipped(DecoupledIO(new MemExuInput())) 385 val out = DecoupledIO(new MemExuOutput()) 386} 387 388class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 389 val io = IO(new MemExeUnitIO) 390 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 391 fu.io.flush := io.flush 392 fu.io.in.valid := io.in.valid 393 io.in.ready := fu.io.in.ready 394 395 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 396 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 397 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 398 fu.io.in.bits.data.imm := io.in.bits.uop.imm 399 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 400 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 401 402 io.out.valid := fu.io.out.valid 403 fu.io.out.ready := io.out.ready 404 405 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 406 io.out.bits.data := fu.io.out.bits.res.data 407 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 408 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 409 io.out.bits.uop.fuType := io.in.bits.uop.fuType 410 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 411 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 412 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 413 414 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 415}