1package xiangshan.backend.decode 2 3import chisel3._ 4import chisel3.util._ 5import freechips.rocketchip.rocket.DecodeLogic 6import xiangshan.backend.decode.Instructions._ 7import xiangshan.{FPUCtrlSignals, XSModule} 8 9class FPDecoder extends XSModule{ 10 val io = IO(new Bundle() { 11 val instr = Input(UInt(32.W)) 12 val fpCtrl = Output(new FPUCtrlSignals) 13 }) 14 15 def X = BitPat("b?") 16 def N = BitPat("b0") 17 def Y = BitPat("b1") 18 val s = BitPat(S) 19 val d = BitPat(D) 20 21 val default = List(X,X,X,X,X,X,X,X,X) 22 23 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 24 val single: Array[(BitPat, List[BitPat])] = Array( 25 FMV_W_X -> List(N,s,d,Y,N,Y,N,N,N), 26 FCVT_S_W -> List(N,s,s,Y,Y,Y,N,N,Y), 27 FCVT_S_WU-> List(N,s,s,Y,Y,Y,N,N,Y), 28 FCVT_S_L -> List(N,s,s,Y,Y,Y,N,N,Y), 29 FCVT_S_LU-> List(N,s,s,Y,Y,Y,N,N,Y), 30 FMV_X_W -> List(N,s,X,N,N,N,N,N,N), 31 FCLASS_S -> List(N,s,X,N,N,N,N,N,N), 32 FCVT_W_S -> List(N,s,X,N,Y,N,N,N,Y), 33 FCVT_WU_S-> List(N,s,X,N,Y,N,N,N,Y), 34 FCVT_L_S -> List(N,s,X,N,Y,N,N,N,Y), 35 FCVT_LU_S-> List(N,s,X,N,Y,N,N,N,Y), 36 FEQ_S -> List(N,s,X,N,Y,N,N,N,N), 37 FLT_S -> List(N,s,X,N,Y,N,N,N,N), 38 FLE_S -> List(N,s,X,N,Y,N,N,N,N), 39 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 40 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 41 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 42 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 43 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 44 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 45 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 46 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 47 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 48 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 49 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 50 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 51 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 52 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 53 ) 54 55 val table = single 56 57 val decoder = DecodeLogic(io.instr, default, table) 58 59 val ctrl = io.fpCtrl 60 val sigs = Seq( 61 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 62 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 63 ctrl.div, ctrl.sqrt, ctrl.fcvt 64 ) 65 sigs.zip(decoder).foreach({case (s, d) => s := d}) 66 ctrl.typ := io.instr(21,20) 67 ctrl.fmt := io.instr(26,25) 68 69 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 70 FADD_S -> List(BitPat("b00"),N,Y), 71 FSUB_S -> List(BitPat("b01"),N,Y), 72 FMUL_S -> List(BitPat("b00"),N,Y), 73 FMADD_S -> List(BitPat("b00"),Y,Y), 74 FMSUB_S -> List(BitPat("b01"),Y,Y), 75 FNMADD_S-> List(BitPat("b11"),Y,Y), 76 FNMSUB_S-> List(BitPat("b10"),Y,Y) 77 ) 78 val fmaDefault = List(BitPat("b??"), N, N) 79 Seq(ctrl.fmaCmd, ctrl.ren3, ctrl.fma).zip( 80 DecodeLogic(io.instr, fmaDefault, fmaTable) 81 ).foreach({ 82 case (s, d) => s := d 83 }) 84} 85