1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.DecodeLogic 23import xiangshan.backend.decode.Instructions._ 24import xiangshan.backend.fu.fpu.FPU 25import xiangshan.{FPUCtrlSignals, XSModule} 26 27class FPDecoder(implicit p: Parameters) extends XSModule{ 28 val io = IO(new Bundle() { 29 val instr = Input(UInt(32.W)) 30 val fpCtrl = Output(new FPUCtrlSignals) 31 }) 32 33 def X = BitPat("b?") 34 def N = BitPat("b0") 35 def Y = BitPat("b1") 36 val s = BitPat(FPU.S) 37 val d = BitPat(FPU.D) 38 val i = BitPat(FPU.D) 39 40 val default = List(X,X,X,N,N,N,X,X,X) 41 42 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 43 val single: Array[(BitPat, List[BitPat])] = Array( 44 // IntToFP 45 FMV_W_X -> List(N,i,s,Y,N,Y,N,N,N), 46 FCVT_S_W -> List(N,i,s,Y,Y,Y,N,N,Y), 47 FCVT_S_WU-> List(N,i,s,Y,Y,Y,N,N,Y), 48 FCVT_S_L -> List(N,i,s,Y,Y,Y,N,N,Y), 49 FCVT_S_LU-> List(N,i,s,Y,Y,Y,N,N,Y), 50 // FPToInt 51 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), // dont box result of fmv.fp.int 52 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 53 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 54 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 55 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 56 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 57 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 58 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 59 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 60 // FPToFP 61 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 62 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 63 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 64 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 65 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 66 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 67 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 68 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 69 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 70 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 71 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 72 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 73 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 74 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 75 ) 76 77 78 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 79 val double: Array[(BitPat, List[BitPat])] = Array( 80 FMV_D_X -> List(N,i,d,Y,N,Y,N,N,N), 81 FCVT_D_W -> List(N,i,d,Y,Y,Y,N,N,Y), 82 FCVT_D_WU-> List(N,i,d,Y,Y,Y,N,N,Y), 83 FCVT_D_L -> List(N,i,d,Y,Y,Y,N,N,Y), 84 FCVT_D_LU-> List(N,i,d,Y,Y,Y,N,N,Y), 85 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 86 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 87 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 88 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 89 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 90 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 91 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 92 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 93 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 94 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 95 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 96 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 97 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 98 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 99 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 100 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 101 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 102 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 103 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 104 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 105 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 106 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 107 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 108 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 109 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 110 ) 111 112 val table = single ++ double 113 114 val decoder = DecodeLogic(io.instr, default, table) 115 116 val ctrl = io.fpCtrl 117 val sigs = Seq( 118 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 119 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 120 ctrl.div, ctrl.sqrt, ctrl.fcvt 121 ) 122 sigs.zip(decoder).foreach({case (s, d) => s := d}) 123 ctrl.typ := io.instr(21, 20) 124 ctrl.fmt := io.instr(26, 25) 125 ctrl.rm := io.instr(14, 12) 126 127 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 128 FADD_S -> List(BitPat("b00"),N), 129 FADD_D -> List(BitPat("b00"),N), 130 FSUB_S -> List(BitPat("b01"),N), 131 FSUB_D -> List(BitPat("b01"),N), 132 FMUL_S -> List(BitPat("b00"),N), 133 FMUL_D -> List(BitPat("b00"),N), 134 FMADD_S -> List(BitPat("b00"),Y), 135 FMADD_D -> List(BitPat("b00"),Y), 136 FMSUB_S -> List(BitPat("b01"),Y), 137 FMSUB_D -> List(BitPat("b01"),Y), 138 FNMADD_S-> List(BitPat("b11"),Y), 139 FNMADD_D-> List(BitPat("b11"),Y), 140 FNMSUB_S-> List(BitPat("b10"),Y), 141 FNMSUB_D-> List(BitPat("b10"),Y) 142 ) 143 val fmaDefault = List(BitPat("b??"), N) 144 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 145 DecodeLogic(io.instr, fmaDefault, fmaTable) 146 ).foreach({ 147 case (s, d) => s := d 148 }) 149} 150